sys_loopback_pl_in_tx.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* sys_loopback_in_tx.uc
 *
 * This file transmits CSIX packets from DRAM. The scratch is read to obtain
 * the DRAM address where the packet to be transmitted is stored. Once it has
 * transmitted a packet it cwaps out and waits for a signal from the receive
 * ME.
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXDP2400
 *  subsystem: DIAG
 *  author: dalsraja, April, 2002
 *  revisions: dalsraja, May 8, 2002
 * 
 * 
 * --------------------------------------------------------------------------
 */

#include "common_uc.h"

#define TX_ENABLE_MASK				0x1
#define TX_MODE						MSF_CSIX
#define TX_WIDTH					MSF_WIDTH_1x32
#define TX_SINGLE_PHY				MSF_SINGLE_PHY
#define TX_ELEMENT_SIZE				MSF_ELEMENTSIZE_128
#define TBUF_ELEM_COUNT				(((1 << (7 - TX_ELEMENT_SIZE)) >> 2) * 3)	// Tot. elements
#define TBUF_ADDR_SHF				(6 + TX_ELEMENT_SIZE)
#define TX_ELEMENTSIZE_BYTE			(1 << TBUF_ADDR_SHF)

#define EXT_HDR						0

#define SRAM_DESC_BASE				0x200000		// 2 Meg onwards
#define DRAM_PCKT_BASE				0x1000000		// 16 Meg onwards

#define ME_NUMBER_RX				0
#define ME_NUMBER_TX				1
#define RX_THD_NUM					0
#define TX_THD_NUM					0
#define INTERTHD_SIG_NUM			15
#define MESSAGE_ADDR				0x200			// For messaging between MEs
#define BUFFER_ADDR_MASK			0xFFFFFF

//#define MAX_PAYLOAD_LENGTH


.reg temp $temp
.reg t0 sramDescBase dramPacketBase pkt_buf_addr loop_count put_ring_num get_ring_num
.reg rx_port_num
.reg MsfAddress MsfAddress0 MsfAddress1
.reg byte_count @packet_count packet_size packet_status sopeop
.reg TxConfigData0
.reg $TxConfigData0
.reg $TxControlWord0 $TxControlWord1
.reg $scratch_data0
.reg tbuf_element
.reg dram_addr tbuf
.reg $prepend_data0 $prepend_data1
.reg $verbose

.sig dram_sig msf_sig interthd_sig cap_sig scratch_sig

.xfer_order $TxControlWord0 $TxControlWord1
.xfer_order $prepend_data0 $prepend_data1

.addr interthd_sig INTERTHD_SIG_NUM
.set_sig interthd_sig

br=ctx[0, init#]
ctx_arb[kill]

init#:
	immed[tbuf_element, 0]
	immed[@packet_count, 0]
	immed[packet_status, 0]
	immed[$prepend_data0, 0]
	alu[get_ring_num, --, B, RING_0, <<2]			// ring number in a register
	alu[put_ring_num, --, B, RING_1, <<2]			// ring number in a register

	immed[sramDescBase, (SRAM_DESC_BASE & MASK_16BIT)]
	immed_w1[sramDescBase, ((SRAM_DESC_BASE >> 16) & MASK_16BIT)]

	immed[dramPacketBase, (DRAM_PCKT_BASE & MASK_16BIT)]
	immed_w1[dramPacketBase, ((DRAM_PCKT_BASE >> 16) & MASK_16BIT)]

.local channel_number
	alu[channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
	alu[t0, channel_number, OR, Q_NUMBER, <<SRAM_Q_ARRAY_NUMBER_FIELD]
.endlocal


//****************************************************
// Configure TX Control
//****************************************************
	immed[tbuf, RBUF_TBUF]
	immed[MsfAddress, MSF_TX_CONTROL]
	immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)]	// put control and data into diff freelist
	immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0 << 1)|(1 << 0))]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
	
	immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 12) | (TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0 << 1)|(1 << 0))]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


//**************************************************
// Configure Scratch Ring
//**************************************************
.begin
	.reg $scratch_base $scratch_head $scratch_tail
	.sig scratch_sig1 scratch_sig2 scratch_sig3

//	immed[$scratch_base,0x200]
	immed[$scratch_head,0]
	immed[$scratch_tail,0]

	alu[$scratch_base, --, B, 0xC, <<28]	// Use ring size of 1024 lw and base 0x0
	cap[write,$scratch_base,SCRATCH_RING_BASE_0],sig_done[scratch_sig1]
	cap[write,$scratch_head,SCRATCH_RING_HEAD_0],sig_done[scratch_sig2]
	cap[write,$scratch_tail,SCRATCH_RING_TAIL_0],sig_done[scratch_sig3]
	ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]

	alu[$scratch_base, --, B, 1, <<12]		// Use ring size of 128 lw and base 0x1000
	cap[write,$scratch_base,SCRATCH_RING_BASE_1],sig_done[scratch_sig1]
	cap[write,$scratch_head,SCRATCH_RING_HEAD_1],sig_done[scratch_sig2]
	cap[write,$scratch_tail,SCRATCH_RING_TAIL_1],sig_done[scratch_sig3]
	ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
.end


//**************************************************
// Send Inter-ME signal to the Receive ME
//**************************************************
	immed[temp, ((ME_NUMBER_RX << 7) | (RX_THD_NUM << 4) | (INTERTHD_SIG_NUM << 0))]
	alu[--, --, B, temp]
	cap[fast_wr, ALU, interthread_sig]

wait_for_assignment#:
	scratch[get, $scratch_data0, get_ring_num, 0, 1], ctx_swap[scratch_sig]
	alu[--, $scratch_data0, -, 0]
	beq[wait_for_assignment#]		// branch to label if there is no new assignment

	alu[pkt_buf_addr, 0, +16, $scratch_data0]
	alu[pkt_buf_addr, --, B, pkt_buf_addr, <<6]
	alu[pkt_buf_addr, pkt_buf_addr, +, dramPacketBase]
	alu[packet_size, --, B, $scratch_data0, >>16]
	alu[packet_size, 0, +8, packet_size]
	alu[rx_port_num, --, B, $scratch_data0, >>24]

transmit#:
	.if (packet_status == 0)
		.if (packet_size <= (TX_ELEMENTSIZE_BYTE - PREPEND_LENGTH))
			alu[byte_count, --, B, packet_size]
			immed[sopeop, SOP_EOP]
		.else
			immed[byte_count, (TX_ELEMENTSIZE_BYTE - PREPEND_LENGTH)]
			immed[sopeop, SOP_NOEOP]
		.endif
	.else
		alu[byte_count, packet_size, -, packet_status]
		.if (byte_count > (TX_ELEMENTSIZE_BYTE - PREPEND_LENGTH))
			immed[byte_count, (TX_ELEMENTSIZE_BYTE - PREPEND_LENGTH)]
			immed[sopeop, MOP]
		.else
			immed[sopeop, NOSOP_EOP]
		.endif
	.endif

	alu[$prepend_data1, sopeop, OR, rx_port_num, <<16]


//****************************************************
// Move data to TBUF
//****************************************************
.begin
	.reg cur_tbuf_addr refcnt

	alu[cur_tbuf_addr, tbuf, OR, tbuf_element, <<TBUF_ADDR_SHF]

	msf[write64, $prepend_data0, cur_tbuf_addr, 0, 1], ctx_swap[msf_sig]

	alu[cur_tbuf_addr, cur_tbuf_addr, +, PREPEND_LENGTH]
	alu[cur_tbuf_addr, --, B, cur_tbuf_addr, <<5]
	alu[cur_tbuf_addr, cur_tbuf_addr, OR, 1, <<4]		// set the overwrite bit for the TBUF addr
	alu[refcnt, --, B, byte_count, >>3]
	alu[--, byte_count, AND, 0x7]
	beq[cont1#]
	alu[refcnt, refcnt, +, 1]			// Calculate the refcnt for indirect ref

cont1#:
	.if (refcnt > 15)		// This is assuming that the RBUF Element are always 128 bytes
		immed[refcnt, 15]
	.endif
	alu[refcnt, --, B, refcnt, <<21]	// Shift to appropriate bit
	alu[refcnt, refcnt, OR, 1, <<25]	// Set the overwrite bit for refcnt

	alu[--, cur_tbuf_addr, OR, refcnt]	// indirect ref
	dram[tbuf_wr, --, pkt_buf_addr, packet_status, 8], indirect_ref, sig_done[dram_sig]
	ctx_arb[dram_sig]	
.end


//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
	.set_sig interthd_sig

	immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]
	alu[MsfAddress, MsfAddress, OR, tbuf_element, <<3]	//TBUF_CTRL_ADDR_SHF

	immed[temp, CSIX_UNICAST]
	alu[temp, temp, OR, PREPEND_LENGTH, <<16]			// prepend length
	alu[$TxControlWord0, temp, OR, byte_count, <<24]		// For Tx Control

	immed[temp, (EXT_HDR & MASK_16BIT)]
	immed_w1[temp, ((EXT_HDR >> 16) & MASK_16BIT)]
	alu[$TxControlWord1, --, B, temp]		// Setting extension header

	msf[write, $TxControlWord0, MsfAddress, 0, 2], ctx_swap[msf_sig]

	alu[packet_status, packet_status, +, byte_count]

	alu[tbuf_element, tbuf_element, +, 1]
	.if (tbuf_element == TBUF_ELEM_COUNT)
		immed[tbuf_element, 0]
	.endif

	.if (packet_size != packet_status)
		br[transmit#]
	.endif

	immed[packet_status, 0]


//*******************************************************
// Free buffer
//*******************************************************
.begin
	.reg temp cellcount buf_addr

	alu[buf_addr, 0, +16, $scratch_data0]
	alu[temp, sramDescBase, +, buf_addr]
	alu[temp, --, B, temp, >>2]

	immed[cellcount, 0x1c, <<16]		// set OV EOP, and SOP
	
	alu[--, cellcount, OR, 0]
	sram[enqueue,  --, t0, temp], indirect_ref
.end

	alu[@packet_count, @packet_count, +, 1]

#ifndef WORKBENCH_SIM
fill#:
	br_inp_state[SCR_Ring1_Full, fill#]
	.local $scratch_data
	alu[$scratch_data, --, B, @packet_count]
	scratch[put, $scratch_data, put_ring_num, 0, 1], ctx_swap[scratch_sig]
	.endlocal
#endif

next_packet#:
	br[wait_for_assignment#]

/*
.begin
	.reg scratch_add $s_xfer

	alu[packet_count, packet_count, +, 1]
	immed[scratch_add, 0x404]
	alu[$s_xfer, --, B, packet_count]
	scratch[write, $s_xfer, scratch_add, 0, 1], ctx_swap[scratch_sig]
.end
*/