sys_loopback_pl_2_eg_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:01:10 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:0xfbfb# 135
:init_rbuf# 38
:init_thread0_only# 20
:l000_01# 94
:l000_end# 94
:l001_01# 104
:l001_02# 113
:l001_03# 122
:l001_04# 131
:l001_end# 132
:l002_01# 102
:l002_end# 103
:l003_01# 111
:l003_end# 112
:l004_01# 120
:l004_end# 121
:l005_01# 129
:l005_end# 130
:next_packet# 134
:null# 134
:rec_error# 144
:receivenextpacket# 77
:rsw# 80
:size_error# 140
*-- no_destination 0
*l0000!cur_me gpr_a_rel 02
*l0000!cur_ctx gpr_b_rel 00
*l0000!sram_channel_number gpr_b_rel 0C
*l0000!t0 gpr_b_rel 0D
*@l0000!total_rx gpr_a_abs 61
;*l0000!rxconfigdata!!2 gpr_a_rel 03
*l0000!rxconfigdata gpr_b_rel 0E
*l0000!rbuf_base gpr_a_rel 00
*l0000!rbuf_elem_done gpr_b_rel 0F
*l0000!rx_thd_freelist gpr_b_rel 01
*l0000!null gpr_b_rel 00
*l0000!elem gpr_b_rel 02
;*l0000!bytecnt!!2 gpr_b_rel 03
*l0000!bytecnt gpr_b_rel 03
*$l0000!prepend_data0 sram_rel 00 0 both 3 0x45
*$l0000!prepend_data1 sram_rel 01 0 both 2 0x45
*$l0000!data_4byte sram_rel 02 0 both 1 0x45
*@l0000!sramdescbase gpr_a_abs 01
*@l0000!drampacketbase gpr_a_abs 11
*@l0000!expected_sequence_0 gpr_a_abs 21
*@l0000!expected_sequence_1 gpr_a_abs 31
*@l0000!expected_sequence_2 gpr_a_abs 41
*@l0000!expected_sequence_3 gpr_a_abs 51
*$l0000!transferreg00 sram_rel 03 0 both 2 0x3B
*$l0000!transferreg01 sram_rel 04 0 both 1 0x3B
*l0001!temp_data gpr_b_rel 01
;*l0002!rxthreadlist!!2 gpr_a_rel 04
;*l0002!rxthreadlist!!3 gpr_b_rel 02
*l0002!rxthreadlist gpr_a_rel 04
*l0002!temp_data gpr_a_rel 05
;*l0002!me_data!!2 gpr_b_rel 04
*l0002!me_data gpr_b_rel 04
*l0003!msfaddress gpr_b_rel 05
*l0003!rxcontroldata gpr_b_rel 06
*$l0003!rxcontroldata sram_rel 00 0 both 1 0x0
*l0004!msfaddress gpr_b_rel 07
*$l0004!csixtypemapdata sram_rel 00 0 both 1 0x0
*l0005!temp_reg gpr_b_rel 05
*l0005!rbufelemdonedata gpr_b_rel 06
*l0006!msfaddress gpr_b_rel 08
*$l0006!rxcontroldata sram_rel 00 0 both 1 0x0
;*l0007!timeout_val!!2 gpr_b_rel 09
*l0007!timeout_val gpr_b_rel 09
*l0008!msfaddress gpr_b_rel 07
*l0008!txcontroldata gpr_b_rel 08
*$l0008!txcontroldata sram_rel 00 0 both 1 0x0
;*l0009!msfaddress!!2 gpr_b_rel 0A
;*l0009!msfaddress!!3 gpr_b_rel 0A
;*l0009!msfaddress!!4 gpr_b_rel 0A
*l0009!msfaddress gpr_b_rel 0A
*l0009!txupcontroldata gpr_b_rel 0B
*$l0009!txupcontroldata sram_rel 00 0 both 1 0x0
*l0010!msfaddress gpr_b_rel 0C
*$l0010!txcontroldata sram_rel 00 0 both 1 0x0
*$l0011!scratch_base sram_rel 00 0 both 1 0x0
*$l0011!scratch_head sram_rel 01 0 both 1 0x0
*$l0011!scratch_tail sram_rel 02 0 both 1 0x0
*l0011!temp_val gpr_b_rel 0D
*l0012!ind_ref_data gpr_b_rel 09
*l0013!rbufaddress gpr_b_rel 0A
*l0014!temp_sequence gpr_b_rel 0B
*l0015!rbuf_elem_done_data gpr_b_rel 0E
*$l0016!temp_scratch sram_rel 00 0 both 2 0x8
*l0016!temp_scratch_addr gpr_b_rel 0F
*$l0016!pkt_num sram_rel 01 0 both 1 0x8
*$l0017!temp_scratch sram_rel 00 0 both 1 0x0
*l0017!temp_scratch_addr gpr_b_rel 00
*$l0018!temp_scratch sram_rel 00 0 both 1 0x0
*l0018!temp_scratch_addr gpr_b_rel 01
*l0011!scratch_sig3 signal 03 0
*l0011!scratch_sig2 signal 02 0
*l0011!scratch_sig1 signal 01 0
*l0000!scratch_sig signal 01 0
*l0000!scratch_sig!!3 signal 01 0
*l0000!scratch_sig!!2 signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!12 signal 01 0
*l0000!msf_sig!!11 signal 01 0
*l0000!msf_sig!!10 signal 01 0
*l0000!msf_sig!!9 signal 01 0
*l0000!msf_sig!!8 signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!next_ctx_sig signal 0E 0
*l0000!rx_sig signal 01 0
.%type R
.%type SI
.%scope global
.%var l0018!temp_scratch_addr 0 R
.%liverange 0 B1 146:147
.%var $l0018!temp_scratch 0 R
.%liverange 0 $W0 145:147
.%liverange 0 $R0 148:148
.%var l0017!temp_scratch_addr 0 R
.%liverange 0 B0 142:143
.%var $l0017!temp_scratch 0 R
.%liverange 0 $W0 141:143
.%liverange 0 $R0 148:148
.%var $l0016!pkt_num 0 R
.%liverange 0 $W1 136:139
.%liverange 0 $R1 148:148
.%var l0016!temp_scratch_addr 0 R
.%liverange 0 B15 138:139
.%var $l0016!temp_scratch 0 R
.%liverange 0 $W0 137:139
.%liverange 0 $R0 148:148
.%var l0015!rbuf_elem_done_data 0 R
.%liverange 0 B14 133:133
.%liverange 0 ~B14 77:132 134:147
.%var l0014!temp_sequence 0 R
.%liverange 0 B11 95:133 135:139 144:147
.%liverange 0 ~B11 77:94 134:134 140:143
.%var l0013!rbufaddress 0 R
.%liverange 0 B10 86:133 135:147
.%liverange 0 ~B10 77:85 134:134
.%var l0012!ind_ref_data 0 R
.%liverange 0 B9 88:133 135:147
.%liverange 0 ~B9 77:87 134:134
.%var l0011!temp_val 0 R
.%liverange 0 B13 70:76
.%liverange 0 ~B13 77:147
.%var $l0011!scratch_tail 0 R
.%liverange 0 $W2 73:76
.%liverange 0 ~$W2 77:147
.%liverange 0 $R2 148:148
.%var $l0011!scratch_head 0 R
.%liverange 0 $W1 72:76
.%liverange 0 ~$W1 77:135 140:147
.%liverange 0 $R1 148:148
.%var $l0011!scratch_base 0 R
.%liverange 0 $W0 71:76
.%liverange 0 ~$W0 77:136 140:140 144:144
.%liverange 0 $R0 148:148
.%var $l0010!txcontroldata 0 R
.%liverange 0 $W0 68:70
.%liverange 0 $R0 67:76
.%liverange 0 ~$R0 77:86 134:134
.%var l0010!msfaddress 0 R
.%liverange 0 B12 66:76
.%liverange 0 ~B12 77:147
.%var $l0009!txupcontroldata 0 R
.%liverange 0 $W0 57:67
.%liverange 0 $R0 148:148
.%var l0009!txupcontroldata 0 R
.%liverange 0 B11 56:76
.%liverange 0 ~B11 77:94 134:134 140:143
.%var l0009!msfaddress 0 R
.%liverange 0 B10 58:76
.%liverange 0 ~B10 77:85 134:134
.%var $l0008!txcontroldata 0 R
.%liverange 0 $W0 54:56
.%liverange 0 $R0 148:148
.%var l0008!txcontroldata 0 R
.%liverange 0 B8 52:76
.%liverange 0 ~B8 77:147
.%var l0008!msfaddress 0 R
.%liverange 0 B7 51:76
.%liverange 0 ~B7 77:147
.%var l0007!timeout_val 0 R
.%liverange 0 B9 48:76
.%liverange 0 ~B9 77:87 134:134
.%var $l0006!rxcontroldata 0 R
.%liverange 0 $W0 46:53
.%liverange 0 $R0 45:66
.%var l0006!msfaddress 0 R
.%liverange 0 B8 44:51
.%var l0005!rbufelemdonedata 0 R
.%liverange 0 B6 39:76
.%liverange 0 ~B6 38:38 77:147
.%var l0005!temp_reg 0 R
.%liverange 0 B5 38:76
.%liverange 0 ~B5 77:147
.%var $l0004!csixtypemapdata 0 R
.%liverange 0 $W0 35:45
.%liverange 0 $R0 148:148
.%var l0004!msfaddress 0 R
.%liverange 0 B7 36:50
.%var $l0003!rxcontroldata 0 R
.%liverange 0 $W0 32:34
.%liverange 0 $R0 148:148
.%var l0003!rxcontroldata 0 R
.%liverange 0 B6 30:37
.%liverange 0 ~B6 38:38
.%var l0003!msfaddress 0 R
.%liverange 0 B5 33:37
.%var l0002!me_data 0 R
.%liverange 0 B4 10:147
.%var l0002!temp_data 0 R
.%liverange 0 A5 11:147
.%var l0002!rxthreadlist 0 R
.%liverange 0 A4 13:14
.%liverange 0 B2 15:76
.%liverange 0 ~B2 77:83 134:134
.%var l0001!temp_data 0 R
.%liverange 0 B1 2:8
.%var $l0000!transferreg01 0 R
.%liverange 0 $W4 148:148
.%liverange 0 $R4 148:148
.%var $l0000!transferreg00 0 R
.%liverange 0 $W3 0:147
.%liverange 0 $R3 0:147
.%var @l0000!expected_sequence_3 0 R
.%liverange 0 @A81 0:147
.%var @l0000!expected_sequence_2 0 R
.%liverange 0 @A65 0:147
.%var @l0000!expected_sequence_1 0 R
.%liverange 0 @A49 0:147
.%var @l0000!expected_sequence_0 0 R