sys_loopback_pl_2_in_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:01:11 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:addfreelist# 64
:init# 6
:init_common# 0
:init_rbuf# 17
:refcnt_calc_done# 118
:wait_for_assignment# 92
:wait_for_next_ctx_sig# 89
:wait_for_sram_sig# 102
:wake_up_next_thread_after_init# 90
*-- no_destination 0
;*l0000!temp!!2 gpr_b_rel 02
;*l0000!temp!!3 gpr_b_rel 02
;*l0000!temp!!4 gpr_b_rel 02
;*l0000!temp!!5 gpr_b_rel 02
;*l0000!temp!!6 gpr_a_rel 07
;*l0000!temp!!7 gpr_b_rel 02
*l0000!temp gpr_b_rel 02
*l0000!txsequenceaddr gpr_b_rel 00
*l0000!byte_count gpr_b_rel 03
*l0000!ring_num gpr_b_rel 04
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x51
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x51
*@l0000!tbuf_element gpr_b_abs 11
*l0000!cur_tbuf_elem gpr_b_rel 05
*l0000!buf_addr gpr_a_rel 01
*l0000!buf_offset gpr_b_rel 06
*l0000!tbuf_base gpr_a_rel 02
;*l0000!cur_tbuf_addr!!2 gpr_b_rel 07
;*l0000!cur_tbuf_addr!!3 gpr_b_rel 07
;*l0000!cur_tbuf_addr!!4 gpr_b_rel 07
*l0000!cur_tbuf_addr gpr_a_rel 03
*l0000!sram_channel_number gpr_b_rel 00
*@l0000!sramdescbase gpr_b_abs 01
*@l0000!drampacketbase gpr_a_abs 04
*l0000!t0 gpr_a_rel 05
*$l0000!prepend_data0 sram_rel 00 0 both 2 0x40
*$l0000!prepend_data1 sram_rel 01 0 both 1 0x40
*l0001!rxcontroldata gpr_b_rel 09
*$l0001!rxcontroldata sram_rel 00 0 both 1 0x0
*l0001!msfaddress gpr_b_rel 0B
*l0002!temp_val gpr_b_rel 0D
*l0002!temp_reg gpr_b_rel 0E
*l0003!rxupcontroldata gpr_b_rel 0C
*$l0003!rxupcontroldata sram_rel 00 0 both 1 0x0
;*l0003!msfaddress!!2 gpr_b_rel 0D
;*l0003!msfaddress!!3 gpr_b_rel 0D
;*l0003!msfaddress!!4 gpr_b_rel 0D
*l0003!msfaddress gpr_b_rel 0D
*$l0004!rxcontroldata sram_rel 00 0 both 1 0x0
*l0004!msfaddress gpr_b_rel 0E
*l0005!msfaddress gpr_b_rel 0F
*l0005!txcontroldata gpr_b_rel 03
*$l0005!txcontroldata sram_rel 00 0 both 1 0x0
;*l0006!timeout_val!!2 gpr_b_rel 0F
*l0006!timeout_val gpr_b_rel 0F
*l0007!cellcount gpr_b_rel 08
*l0007!freelist gpr_b_rel 09
*$l0007!s0 sram_rel 00 0 both 3 0x22
*$l0007!s1 sram_rel 01 0 both 2 0x22
*$l0007!s2 sram_rel 02 0 both 1 0x22
;*l0007!tmp!!2 gpr_b_rel 0A
;*l0007!tmp!!3 gpr_b_rel 0A
;*l0007!tmp!!4 gpr_b_rel 0A
*l0007!tmp gpr_a_rel 09
*$l0007!sr0 sram_rel 00 0 both 4 0x16
*$l0007!sr1 sram_rel 01 0 both 3 0x16
*$l0007!sr2 sram_rel 02 0 both 2 0x16
*$l0007!sr3 sram_rel 03 0 both 1 0x16
*l0007!sram_desc_base gpr_b_rel 05
*$l0008!scratch_base sram_rel 00 0 both 1 0x0
*$l0008!scratch_head sram_rel 01 0 both 1 0x0
*$l0008!scratch_tail sram_rel 02 0 both 1 0x0
*$l0009!scratch_data sram_rel 00 0 both 1 0x0
*$l0010!sram_data sram_rel 00 0 both 1 0x0
;*l0011!refcnt!!2 gpr_a_rel 06
;*l0011!refcnt!!3 gpr_a_rel 06
*l0011!refcnt gpr_a_rel 06
;*l0011!pkt_buf_addr!!2 gpr_a_rel 00
*l0011!pkt_buf_addr gpr_b_rel 0B
;*l0012!msfaddress!!2 gpr_b_rel 0C
*l0012!msfaddress gpr_a_rel 08
*l0013!temp gpr_b_rel 06
*l0013!cellcount gpr_b_rel 08
*l0008!scratch_sig3 signal 03 0
*l0008!scratch_sig2 signal 02 0
*l0008!scratch_sig1 signal 01 0
*l0007!qa_init signal 01 0
*l0007!qa_init!!2 signal 01 0
*l0000!next_ctx_sig signal 0E 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!11 signal 01 0
*l0000!msf_sig!!10 signal 01 0
*l0000!msf_sig!!9 signal 01 0
*l0000!msf_sig!!8 signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!scratch_sig signal 01 0
*l0000!sram_sig signal 01 0
*l0000!dram_sig signal 02 0
.%type R
.%type SI
.%scope global
.%var l0013!cellcount 0 R
.%liverange 0 B8 134:136
.%liverange 0 ~B8 92:133
.%var l0013!temp 0 R
.%liverange 0 B6 133:136
.%liverange 0 ~B6 92:103
.%var l0012!msfaddress 0 R
.%liverange 0 A8 124:124
.%liverange 0 B12 125:136
.%liverange 0 ~B12 92:123
.%var l0011!pkt_buf_addr 0 R
.%liverange 0 B11 110:110
.%liverange 0 A0 111:136
.%liverange 0 ~A0 92:109
.%var l0011!refcnt 0 R
.%liverange 0 A6 115:136
.%liverange 0 ~A6 92:114
.%var $l0010!sram_data 0 R
.%liverange 0 $W0 137:137
.%liverange 0 $R0 97:136
.%liverange 0 ~$R0 92:92
.%var $l0009!scratch_data 0 R
.%liverange 0 $W0 137:137
.%liverange 0 $R0 93:96
.%liverange 0 ~$R0 92:92
.%var $l0008!scratch_tail 0 R
.%liverange 0 $W2 72:88
.%liverange 0 ~$W2 90:136
.%liverange 0 $R2 137:137
.%var $l0008!scratch_head 0 R
.%liverange 0 $W1 71:88
.%liverange 0 ~$W1 90:106
.%liverange 0 $R1 137:137
.%var $l0008!scratch_base 0 R
.%liverange 0 $W0 70:88
.%liverange 0 ~$W0 90:105
.%liverange 0 $R0 137:137
.%var l0007!sram_desc_base 0 R
.%liverange 0 B5 50:88
.%liverange 0 ~B5 90:97
.%var $l0007!sr3 0 R
.%liverange 0 $W3 137:137
.%liverange 0 $R3 137:137
.%var $l0007!sr2 0 R
.%liverange 0 $W2 137:137
.%liverange 0 $R2 137:137
.%var $l0007!sr1 0 R
.%liverange 0 $W1 137:137
.%liverange 0 $R1 137:137
.%var $l0007!sr0 0 R
.%liverange 0 $W0 137:137
.%liverange 0 $R0 60:88
.%liverange 0 ~$R0 90:92
.%var l0007!tmp 0 R
.%liverange 0 A9 52:52
.%liverange 0 B10 53:88
.%liverange 0 ~B10 90:136
.%var $l0007!s2 0 R
.%liverange 0 $W2 56:71
.%liverange 0 $R2 137:137
.%var $l0007!s1 0 R
.%liverange 0 $W1 55:70
.%liverange 0 $R1 137:137
.%var $l0007!s0 0 R
.%liverange 0 $W0 54:69
.%liverange 0 $R0 137:137
.%var l0007!freelist 0 R
.%liverange 0 B9 62:88
.%liverange 0 ~B9 90:136
.%var l0007!cellcount 0 R
.%liverange 0 B8 64:88
.%liverange 0 ~B8 90:133
.%var l0006!timeout_val 0 R
.%liverange 0 B15 44:88
.%liverange 0 ~B15 90:136
.%var $l0005!txcontroldata 0 R
.%liverange 0 $W0 40:53
.%liverange 0 $R0 137:137
.%var l0005!txcontroldata 0 R
.%liverange 0 B3 38:88
.%liverange 0 ~B3 90:104
.%var l0005!msfaddress 0 R
.%liverange 0 B15 37:43
.%var l0004!msfaddress 0 R
.%liverange 0 B14 33:88
.%liverange 0 ~B14 90:136
.%var $l0004!rxcontroldata 0 R
.%liverange 0 $W0 35:39
.%liverange 0 $R0 34:59
.%var l0003!msfaddress 0 R
.%liverange 0 B13 25:88
.%liverange 0 ~B13 90:136
.%var $l0003!rxupcontroldata 0 R
.%liverange 0 $W0 24:34
.%liverange 0 $R0 137:137
.%var l0003!rxupcontroldata 0 R
.%liverange 0 B12 23:88
.%liverange 0 ~B12 90:124
.%var l0002!temp_reg 0 R
.%liverange 0 B14 18:32
.%liverange 0 ~B14 17:17
.%var l0002!temp_val 0 R
.%liverange 0 B13 17:24
.%var l0001!msfaddress 0 R
.%liverange 0 B11 15:88
.%liverange 0 ~B11 90:109
.%var $l0001!rxcontroldata 0 R
.%liverange 0 $W0 14:23
.%liverange 0 $R0 137:137
.%var l0001!rxcontroldata 0 R
.%liverange 0 B9 12:61
.%var $l0000!prepend_data1 0 R
.%liverange 0 $W1 107:130
.%liverange 0 $R1 137:137
.%var $l0000!prepend_data0 0 R
.%liverange 0 $W0 106:127
.%liverange 0 $R0 137:137
.%var l0000!t0 0 R
.%liverange 0 A5 5:136
.%var @l0000!drampacketbase 0 R
.%liverange 0 @A4 0:136
.%var @l0000!sramdescbase 0 R
.%liverange 0 @B1 0:136
.%var l0000!sram_channel_number 0 R
.%liverange 0 B0 4:136
.%var l0000!cur_tbuf_addr 0 R
.%liverange 0 A3 108:111
.%liverange 0 B7 112:136
.%liverange 0 ~B7 92:107
.%var l0000!tbuf_base 0 R
.%liverange 0 A2 3:136
.%var l0000!buf_offset 0 R
.%liverange 0 B6 104:132
.%var l0000!buf_addr 0 R
.%liverange 0 A1 96:136
.%liverange 0 ~A1 92:95
.%var l0000!cur_tbuf_elem 0 R
.%liverange 0 B5 98:136
.%liverange 0 ~B5 92:97
.%var @l0000!tbuf_element 0 R
.%liverange 0 @B17 0:136
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 131:136
.%liverange 0 ~$W1 92:106
.%liverange 0 $R1 137:137
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 128:136
.%liverange 0 ~$W0 92:105
.%liverange 0 $R0 137:137
.%var l0000!ring_num 0 R
.%liverange 0 B4 2:136
.%var l0000!byte_count 0 R
.%liverange 0 B3 105:136
.%liverange 0 ~B3 92:104
.%var l0000!txsequenceaddr 0 R
.%liverange 0 B0 1:3
.%var l0000!temp 0 R
.%liverange 0 B2 77:88 126:126 129:136
.%liverange 0 ~B2 90:125
.%liverange 0 A7 127:128
.%var l0008!scratch_sig3 1 R
.%liverange 0 G3 75:76
.%var l0008!scratch_sig2 1 R
.%liverange 0 G2 74:76
.%var l0008!scratch_sig1 1 R
.%liverange 0 G1 73:76
.%var l0007!qa_init 1 R
.%liverange 0 G1 57:57 60:60
.%var l0000!next_ctx_sig 1 R
.%liverange 0 G14 89:90
.%var l0000!msf_sig 1 R