line_rate_pl_eg_rx.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

	.reg $scratch_base $scratch_head $scratch_tail temp_val
	.sig scratch_sig1 scratch_sig2 scratch_sig3

	alu[temp_val, --, B, RINGBASE_256_0, <<9]
	alu[$scratch_base, temp_val, OR, RINGSIZE_256, <<30]	// Use ring size of 256 lw and base 0x0
	immed[$scratch_head,0]
	immed[$scratch_tail,0]

	cap[write,$scratch_base,SCRATCH_RING_BASE_0],sig_done[scratch_sig1]
	cap[write,$scratch_head,SCRATCH_RING_HEAD_0],sig_done[scratch_sig2]
	cap[write,$scratch_tail,SCRATCH_RING_TAIL_0],sig_done[scratch_sig3]
	ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]

	alu[temp_val, --, B, RINGBASE_256_1, <<9]
	alu[$scratch_base, temp_val, OR, RINGSIZE_256, <<30]	// Use ring size of 256 lw and base 0x0
	immed[$scratch_head,0]
	immed[$scratch_tail,0]

	cap[write,$scratch_base,SCRATCH_RING_BASE_1],sig_done[scratch_sig1]
	cap[write,$scratch_head,SCRATCH_RING_HEAD_1],sig_done[scratch_sig2]
	cap[write,$scratch_tail,SCRATCH_RING_TAIL_1],sig_done[scratch_sig3]
	ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]

	alu[temp_val, --, B, RINGBASE_256_2, <<9]
	alu[$scratch_base, temp_val, OR, RINGSIZE_256, <<30]	// Use ring size of 256 lw and base 0x0
	immed[$scratch_head,0]
	immed[$scratch_tail,0]

	cap[write,$scratch_base,SCRATCH_RING_BASE_2],sig_done[scratch_sig1]
	cap[write,$scratch_head,SCRATCH_RING_HEAD_2],sig_done[scratch_sig2]
	cap[write,$scratch_tail,SCRATCH_RING_TAIL_2],sig_done[scratch_sig3]
	ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]

	alu[temp_val, --, B, RINGBASE_256_3, <<9]
	alu[$scratch_base, temp_val, OR, RINGSIZE_256, <<30]	// Use ring size of 256 lw and base 0x0
	immed[$scratch_head,0]
	immed[$scratch_tail,0]

	cap[write,$scratch_base,SCRATCH_RING_BASE_3],sig_done[scratch_sig1]
	cap[write,$scratch_head,SCRATCH_RING_HEAD_3],sig_done[scratch_sig2]
	cap[write,$scratch_tail,SCRATCH_RING_TAIL_3],sig_done[scratch_sig3]
	ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
.end


//****************************************************
// Configure RX/TX Control
//****************************************************
.begin
	.reg MsfAddress RxControlData $RxControlData
	immed[MsfAddress, MSF_RX_CONTROL]
	msf[read, $RxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
	alu[$RxControlData, $RxControlData, OR, EG_RX_ENABLE_MASK, <<28]
	msf[write, $RxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end


//****************************************************
// Configure TX Control
//****************************************************
.begin
	.reg MsfAddress TxControlData $TxControlData
	immed[MsfAddress, MSF_TX_CONTROL]
	msf[read, $TxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
	alu[$TxControlData, $TxControlData, OR, EG_TX_ENABLE_MASK, <<28]
	msf[write, $TxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end


//**************************************************
// Signal Transmit MEs
//**************************************************
.local temp
	immed[temp, ((EG_ME_NUMBER_TX_0 << 7) | (EG_SIG_THD_NUM << 4) | (EG_INTER_ME_SIG_NUM << 0))]
	alu[--, --, B, temp]
	cap[fast_wr, ALU, interthread_sig]	// to signal Tx ME that Rx has finished its init

	immed[temp, ((EG_ME_NUMBER_TX_1 << 7) | (EG_SIG_THD_NUM << 4) | (EG_INTER_ME_SIG_NUM << 0))]
	alu[--, --, B, temp]
	cap[fast_wr, ALU, interthread_sig]	// to signal Rx ME that Tx has finished its init

	immed[temp, ((EG_ME_NUMBER_TX_2 << 7) | (EG_SIG_THD_NUM << 4) | (EG_INTER_ME_SIG_NUM << 0))]
	alu[--, --, B, temp]
	cap[fast_wr, ALU, interthread_sig]	// to signal Tx ME that Rx has finished its init

	immed[temp, ((EG_ME_NUMBER_TX_3 << 7) | (EG_SIG_THD_NUM << 4) | (EG_INTER_ME_SIG_NUM << 0))]
	alu[--, --, B, temp]
	cap[fast_wr, ALU, interthread_sig]	// to signal Rx ME that Tx has finished its init
.endlocal


ReceiveNextPacket#:
	local_csr_wr[SAME_ME_SIGNAL, NEXT_CTX_SIG_DATA]
	msf[fast_wr, --, Rx_Thd_Freelist, RxConfigData] // add thread to freelist
	.set_sig rx_sig next_ctx_sig
	ctx_arb[rx_sig, next_ctx_sig]	


// RSW should be in xfer register
// Transfer RBUF data to sram_in transfer registers
//***************************************
// Extract RSW
//***************************************
RSW#:
	alu[null, 0x1, AND, $TransferReg00, >>9]		// Extract null
	bne[NULL#]										// If null=1, result=0

//	alu[error, 0x1, AND, $TransferReg00, >>13]

	sram[dequeue, $sr0, t0, 0], sig_done[sram_sig]	// Get a buffer from the queue

	alu[elem, 0xFF, AND, $TransferReg00, >>24]		// RBUF element number

.begin
	.reg refcnt ind_ref_data

.local RBufAddress
	alu[RBufAddress, RBuf_Base, OR, elem, <<EG_RBUF_ADDR_SHF]
	msf[read64, $prepend_data0, RBufAddress, 0, 1], sig_done[msf_sig]	// Extract prepend data
	alu[ind_ref_data, RBufAddress, +, PREPEND_LENGTH]	// Calc. RBuf address for packet data
.endlocal		// RBufAddress

	local_csr_wr[SAME_ME_SIGNAL, NEXT_CTX_SIG_DATA]

	alu[bytecnt, 0xFF, AND, $TransferReg00, >>16]	// Extract byte count
	alu[bytecnt, bytecnt, -, PREPEND_LENGTH]		// Subtract prepend data length

//****************************************************
// Calculate the reference count for dram[rbuf_rd...]
//****************************************************
	alu[refcnt, --, B, bytecnt, >>3]
	alu[--, bytecnt, AND, 0x7]
	bne[set_refcnt_overwrite_bit#]
	alu[refcnt, refcnt, -, 1]
set_refcnt_overwrite_bit#:
	alu[refcnt, refcnt, OR, 1, <<4]		// Set the overwrite bit for refcnt

	.set_sig next_ctx_sig
	ctx_arb[sram_sig, msf_sig, next_ctx_sig], defer[1]
	alu[ind_ref_data, (1 << 4), OR, ind_ref_data, <<5]	// shift rbuf addr and set the overwrite bit

.local pkt_buff_addr rel freebuffer bdptr ring_data $sram_data
//*************************************************************
// Calculate packet buffer address where packet will be stored
//*************************************************************
	alu[freebuffer, --, B, $sr0, <<2]		// Shift 2 as address obtained is longword address
	alu[rel, freebuffer, -, @sramDescBase]
	alu[rel, --, B, rel, <<5]
	alu[pkt_buff_addr, @dramPacketBase, +, rel]	


	local_csr_wr[SAME_ME_SIGNAL, NEXT_CTX_SIG_DATA]		// Signal next ctx

//****************************************************
// Move from RBUF to DRAM
//****************************************************
	alu[ind_ref_data, ind_ref_data, OR, refcnt, <<21]	// shift refcnt and add for indirect ref
	dram[rbuf_rd, --, pkt_buff_addr, 0, 8], indirect_ref, sig_done[dram_sig]


//****************************************************
// Put packet info in SRAM
//****************************************************
	alu[$sram_data, --, B, bytecnt]
	sram[write, $sram_data, freebuffer, sram_channel_number, 1], sig_done[sram_sig]

	.set_sig next_ctx_sig
	ctx_arb[sram_sig, next_ctx_sig], defer[1]
	alu[$ring_data, --, B, freebuffer]

wait_for_dram_sig#:
	.set_sig next_ctx_sig
	br_signal[dram_sig, rbuf_to_dram_done#]
	local_csr_wr[SAME_ME_SIGNAL, NEXT_CTX_SIG_DATA]
	ctx_arb[next_ctx_sig]
	br[wait_for_dram_sig#]
.endlocal		// pkt_buff_addr rel freebuffer bdptr ring_data $sram_data
.end

rbuf_to_dram_done#:
.local jump_offset
	alu[jump_offset, --, B, $prepend_data0, <<2]
	jump[jump_offset, port0#], targets[port0#, port1#, port2#, port3#]
.endlocal

port0#:
	alu[ring, --, B, RING_0, <<2]
check_ring0_full#:
	br_inp_state[SCR_Ring0_Full, check_ring0_full#]
	br[put_data_to_scratch#]
	nop

port1#:
	alu[ring, --, B, RING_1, <<2]
check_ring1_full#:
	br_inp_state[SCR_Ring1_Full, check_ring1_full#]
	br[put_data_to_scratch#]
	nop

port2#:
	alu[ring, --, B, RING_2, <<2]
check_ring2_full#:
	br_inp_state[SCR_Ring2_Full, check_ring2_full#]
	br[put_data_to_scratch#]
	nop

port3#:
	alu[ring, --, B, RING_3, <<2]
check_ring3_full#:
	br_inp_state[SCR_Ring3_Full, check_ring3_full#]


//	alu[ring, --, B, $prepend_data0, <<2]

//****************************************************
// Put buffer address in scratch ring
//****************************************************
put_data_to_scratch#:
	scratch[put, $ring_data, ring, 0, 1], sig_done[scratch_sig]

	local_csr_wr[SAME_ME_SIGNAL, NEXT_CTX_SIG_DATA]


//**************************************************************
//  Free up Element by writing to RBUF_Element_Done
//**************************************************************
.begin
	.reg rbuf_elem_done_data
	alu[rbuf_elem_done_data, --, B, elem, <<16]
	msf[fast_wr, --, rbuf_elem_done_data, RBUF_ELEMENT_DONE]
.end

	.set_sig next_ctx_sig
	ctx_arb[scratch_sig, next_ctx_sig]

NULL#:
next_packet#:
	br[ReceiveNextPacket#]			// loop around and wait for next packet