line_rate_pl_eg_rx.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* line_rate_bw_eg_rx.uc
 *
 *
 *
 * NOTE: THIS IS NOT A PERFORMANCE BENCHMARK!!!! IT IS JUST TO CHECK IF THE
 *       HARDWARE IS ABLE TO HANDLE DATA AT THE LINERATE THAT IS BEING
 *       PUMPED INTO THE SYSTEM
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXDP2400
 *  subsystem: DIAG
 *  author: dalsraja, November 11, 2002
 *  revisions:
 * 
 * 
 * --------------------------------------------------------------------------
 */

#include "common_uc.h"
#include "line_rate_pl.h"

#define RX_TRANSFER_THREAD				&$TransferReg00
#define RX_SIGNAL						&rx_sig

#define NEXT_CTX_SIGNAL_NUM				EG_SAME_ME_SIG_NUM
#define NEXT_CTX_SIG_DATA				((1 << 7) | (NEXT_CTX_SIGNAL_NUM << 3))

.reg cur_me cur_ctx
.reg sram_channel_number t0 $sr0
.reg ring
.reg RxConfigData
.reg RBuf_Base Rbuf_Elem_Done Rx_Thd_Freelist
.reg null error elem bytecnt
.reg $prepend_data0 $prepend_data1
.reg $ring_data
.reg @sramDescBase @dramPacketBase
.reg $TransferReg00 $TransferReg01
.sig rx_sig
.sig next_ctx_sig
.sig msf_sig scratch_sig sram_sig dram_sig

.xfer_order $TransferReg00 $TransferReg01
.xfer_order $prepend_data0 $prepend_data1

.addr next_ctx_sig EG_SAME_ME_SIG_NUM

.set $TransferReg00

.begin
	.reg temp_data
	local_csr_rd[ACTIVE_CTX_STS]
	immed[temp_data, 0]
	alu[cur_me, 0x1F, AND, temp_data, >>3]		// Extract the current ME number
	alu[cur_ctx, 0x7, AND, temp_data]			// Extract the current context number
.end

	alu[sram_channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
	alu[t0, sram_channel_number, OR, Q_NUMBER, <<SRAM_Q_ARRAY_NUMBER_FIELD]

	immed[RBuf_Base, RBUF_TBUF ]
	immed[Rbuf_Elem_Done, RBUF_ELEMENT_DONE]
	immed[Rx_Thd_Freelist, RX_THREAD_FREELIST_0]

.begin
	.reg RxThreadList temp_data me_data
	alu[me_data, 0x3, AND, cur_me]
	alu[temp_data, --, B, cur_me, >>4]
	alu[me_data, me_data, OR, temp_data, <<2]
	immed[RxThreadList, (RX_SIGNAL << 12)]
	alu[RxThreadList, RxThreadList, OR, me_data, <<7]
	alu[RxThreadList, RxThreadList, OR, cur_ctx, <<4]
	alu[RxConfigData, RxThreadList,  OR , RX_TRANSFER_THREAD]
	alu[RxConfigData, --,  B, RxConfigData, <<16]		// Shift 16 for msf[fast_wr...]
.end

	br=ctx[0, init_thread0_only#]
	.set_sig next_ctx_sig
	ctx_arb[next_ctx_sig]
	br[ReceiveNextPacket#]


init_thread0_only#:
	immed[@sramDescBase, (EG_SRAM_DESC_BASE & MASK_16BIT)]
	immed_w1[@sramDescBase, ((EG_SRAM_DESC_BASE >> 16) & MASK_16BIT)]

	immed[@dramPacketBase, (EG_DRAM_PCKT_BASE & MASK_16BIT)]
	immed_w1[@dramPacketBase, ((EG_DRAM_PCKT_BASE >> 16) & MASK_16BIT)]


//****************************************************
// Configure RX/TX Control
//****************************************************
.begin
	.reg MsfAddress RxControlData $RxControlData
	immed[RxControlData, ((0<<9) | (EG_RX_ELEMENT_SIZE << 2))] // put control and data into diff freelist
	immed_w1[RxControlData, ((EG_RX_MODE << 6) | (EG_RX_WIDTH << 4) | (EG_RX_PHY << 3) | (0 << 1) | (1 << 0))]
	alu[$RxControlData, --, B, RxControlData]
	immed[MsfAddress, MSF_RX_CONTROL]
	msf[write, $RxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end


//****************************************************
// Configure CSIX_TYPE_MAP
//****************************************************
.begin
	.reg MsfAddress $CsixTypeMapData
	alu[$CsixTypeMapData, --, B, MSF_CSIX_RBUF_DATA, <<BIT_SHF_UNICAST]
	immed[MsfAddress, CSIX_TYPE_MAP]
	msf[write, $CsixTypeMapData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end


//******************************************************
// Initialize RBUF Freelist to add elements to the list
//******************************************************
.begin
	.reg temp_reg RbufElemDoneData

	immed[temp_reg, 0]

init_RBUF#:
	alu[RbufElemDoneData, --, B, temp_reg, <<16]
	msf[fast_wr, --, RbufElemDoneData, RBUF_ELEMENT_DONE]
	alu[temp_reg, temp_reg, +, 1]
	alu[--, EG_RBUF_ELEM_COUNT, -, temp_reg]
	bne[init_RBUF#]
.end


//******************************************************
// Configure Rx_Thread_Freelist_Timeout0
//******************************************************
.begin
	.reg timeout_val
	immed[timeout_val, FREELIST_TIMEOUT_VAL]			// timeout value
	alu[timeout_val,--, B, timeout_val, <<16]			// Shift 16 for fast_wr
	msf[fast_wr, --, timeout_val, RX_THREAD_FREELIST_TIMEOUT_0]
.end


//****************************************************
// Configure TX Control
//****************************************************
.begin
	.reg MsfAddress TxControlData $TxControlData
	immed[MsfAddress, MSF_TX_CONTROL]
	immed[TxControlData, (EG_TX_ELEMENTSIZE << 2)]	// put control and data into diff freelist
	immed_w1[TxControlData, ((EG_TX_ENABLE_MASK << 8) | (EG_TX_MODE << 6) | (EG_TX_WIDTH << 4) | (EG_TX_PHY << 3) | (0<<1)|(1<<0))]
	alu[$TxControlData, --, B, TxControlData]
	msf[write, $TxControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end


//******************************************************
// Configure Tx UP Control
//******************************************************
.begin
	.reg MsfAddress TxUPControlData $TxUPControlData
	immed[TxUPControlData, (UP_CTRL_CP_MODE | UP_CTRL_PARITY_ODD | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
//	immed[TxUPControlData, (UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
	alu[$TxUPControlData, --, B, TxUPControlData]

	immed[MsfAddress, TX_UP_CONTROL_0]
	msf[write, $TxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
	immed[MsfAddress, TX_UP_CONTROL_1]
	msf[write, $TxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
	immed[MsfAddress, TX_UP_CONTROL_2]
	msf[write, $TxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
	immed[MsfAddress, TX_UP_CONTROL_3]
	msf[write, $TxUPControlData, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end


//****************************************************
// Set up the freelist (queue)
//****************************************************
.begin
	.reg cellcount freelist sr0
	.reg $s0 $s1 $s2
	.reg tmp
	.sig qa_init addr
	.reg $sr0 $sr1 $sr2 $sr3
	.reg sram_desc_base
	.xfer_order $sr0 $sr1 $sr2 $sr3
	.xfer_order $s0 $s1 $s2

	immed[sram_desc_base, (EG_SRAM_DESC_BASE & MASK_16BIT)]
	immed_w1[sram_desc_base, ((EG_SRAM_DESC_BASE >> 16) & MASK_16BIT)]

	alu[tmp, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
	alu[tmp, tmp, OR, sram_desc_base]
	immed[$s0, 0]
	immed[$s1, 0]
	immed[$s2, 0]
	
	sram[write, $s0, tmp, 0, 3], ctx_swap[qa_init]
	
	alu[tmp, --, B, sram_desc_base]
	alu[tmp, --, B, tmp, >>2]
	sram[rd_qdesc_head, $sr0, t0, tmp, 2], ctx_swap[qa_init]
	sram[rd_qdesc_other, --, t0, tmp]

	immed[freelist, (FREELIST_SIZE & MASK_16BIT)]
	immed_w1[freelist, ((FREELIST_SIZE >> 16) & MASK_16BIT)]
	 
	immed[cellcount, 0x1c, <<16]		//set cell count to 1, set OV EOP, and SOP
	
addfreelist#:
	alu[--, cellcount, OR, 0]
	sram[enqueue,  --, t0, tmp], indirect_ref
	alu[tmp, tmp, +, 1]
	alu[freelist, freelist, -, 1]
	bne[addfreelist#]
.end


//**************************************************
// Configure Scratch Ring
//**************************************************
.begin