line_rate_pl_in_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:03:20 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:check_ring_full# 81
:init_done# 37
:init_thread0_only# 29
:l000_01# 8
:l000_02# 12
:l000_03# 16
:l000_end# 17
:l001_01# 63
:l001_end# 64
:next_packet# 86
:null# 86
:rbuf_to_dram_done# 80
:receivenextpacket# 39
:rsw# 42
:set_refcnt_overwrite_bit# 53
:startreceive# 39
:wait_for_dram_sig# 76
:wait_for_inter_me_sig# 36
*-- no_destination 0
*l0000!cur_me gpr_a_rel 08
*l0000!cur_ctx gpr_a_rel 09
*l0000!sram_channel_number gpr_a_rel 00
*l0000!t0 gpr_b_rel 02
*l0000!ring gpr_a_rel 01
;*l0000!rxconfigdata!!2 gpr_a_rel 02
*l0000!rxconfigdata gpr_b_rel 0D
*$l0000!transferreg00 sram_rel 00 0 both 2 0x27
*$l0000!transferreg01 sram_rel 01 0 both 1 0x27
*l0000!rbuf_base gpr_b_rel 03
*l0000!rbuf_elem_done gpr_b_rel 0E
*l0000!rx_thd_freelist gpr_b_rel 04
*l0000!null gpr_b_rel 0F
*l0000!elem gpr_b_rel 05
*l0000!bytecnt gpr_a_rel 03
*l0000!rx_port_num gpr_b_rel 09
*$l0000!sr0 sram_rel 01 0 both 1 0x0
*$l0000!ring_data sram_rel 00 0 both 1 0x0
*@l0000!sramdescbase gpr_a_abs 04
*@l0000!drampacketbase gpr_a_abs 14
*@l0000!half_duplex gpr_b_abs 06
*l0001!temp gpr_b_rel 02
;*l0002!rxthreadlist!!2 gpr_b_rel 00
;*l0002!rxthreadlist!!3 gpr_b_rel 00
*l0002!rxthreadlist gpr_b_rel 00
*l0003!duplex_addr gpr_b_rel 01
*$l0003!duplex sram_rel 01 0 both 1 0x0
;*l0004!refcnt!!2 gpr_a_rel 05
*l0004!refcnt gpr_b_rel 0A
;*l0004!ind_ref_data!!2 gpr_b_rel 07
;*l0004!ind_ref_data!!3 gpr_b_rel 07
*l0004!ind_ref_data gpr_b_rel 07
*l0004!dest_port_num gpr_b_rel 0B
*$l0004!sram_data sram_rel 01 0 both 1 0x0
*l0005!rbufoffset gpr_a_rel 06
*l0006!bit0 gpr_a_rel 07
*l0006!bit1 gpr_b_rel 0C
*l0007!pkt_buff_addr gpr_b_rel 00
;*l0007!rel!!2 gpr_b_rel 08
*l0007!rel gpr_b_rel 08
*l0007!freebuffer gpr_b_rel 01
*l0008!rbuf_elem_done_data gpr_b_rel 05
*l0000!dram_sig signal 02 0
*l0000!sram_sig signal 01 0
*l0000!sram_sig!!2 signal 01 0
*l0000!scratch_sig signal 01 0
*l0000!scratch_sig!!2 signal 01 0
*l0000!inter_me_sig signal 0F 0
*l0000!same_me_sig signal 0E 0
*l0000!rx_sig signal 01 0
.%type R
.%type SI
.%scope global
.%var l0008!rbuf_elem_done_data 0 R
.%liverange 0 B5 84:85
.%liverange 0 ~B5 39:46 86:86
.%var l0007!freebuffer 0 R
.%liverange 0 B1 68:85
.%liverange 0 ~B1 39:67 86:86
.%var l0007!rel 0 R
.%liverange 0 B8 69:85
.%liverange 0 ~B8 39:68 86:86
.%var l0007!pkt_buff_addr 0 R
.%liverange 0 B0 71:85
.%liverange 0 ~B0 39:70 86:86
.%var l0006!bit1 0 R
.%liverange 0 B12 60:62
.%liverange 0 ~B12 39:59 63:86
.%var l0006!bit0 0 R
.%liverange 0 A7 59:62
.%liverange 0 ~A7 39:58 63:86
.%var l0005!rbufoffset 0 R
.%liverange 0 A6 55:85
.%liverange 0 ~A6 39:54 86:86
.%var $l0004!sram_data 0 R
.%liverange 0 $W1 62:62 64:85
.%liverange 0 ~$W1 39:61 63:63 86:86
.%liverange 0 $R1 87:87
.%var l0004!dest_port_num 0 R
.%liverange 0 B11 61:62
.%liverange 0 ~B11 39:60 63:86
.%var l0004!ind_ref_data 0 R
.%liverange 0 B7 56:85
.%liverange 0 ~B7 39:55 86:86
.%var l0004!refcnt 0 R
.%liverange 0 B10 50:53
.%liverange 0 A5 54:85
.%liverange 0 ~A5 39:49 86:86
.%var $l0003!duplex 0 R
.%liverange 0 $W1 87:87
.%liverange 0 $R1 35:36
.%liverange 0 ~$R1 37:45 86:86
.%var l0003!duplex_addr 0 R
.%liverange 0 B1 34:36
.%liverange 0 ~B1 37:67 86:86
.%var l0002!rxthreadlist 0 R
.%liverange 0 B0 23:38
.%liverange 0 ~B0 39:70 86:86
.%var l0001!temp 0 R
.%liverange 0 B2 2:19
.%var @l0000!half_duplex 0 R
.%liverange 0 @B6 0:86
.%var @l0000!drampacketbase 0 R
.%liverange 0 @A20 0:86
.%var @l0000!sramdescbase 0 R
.%liverange 0 @A4 0:86
.%var $l0000!ring_data 0 R
.%liverange 0 $W0 76:85
.%liverange 0 ~$W0 39:75 86:86
.%liverange 0 $R0 87:87
.%var $l0000!sr0 0 R
.%liverange 0 $W1 87:87
.%liverange 0 $R1 46:85
.%liverange 0 ~$R1 39:45 86:86
.%var l0000!rx_port_num 0 R
.%liverange 0 B9 49:85
.%liverange 0 ~B9 39:48 86:86
.%var l0000!bytecnt 0 R
.%liverange 0 A3 48:85
.%liverange 0 ~A3 39:47 86:86
.%var l0000!elem 0 R
.%liverange 0 B5 47:83
.%var l0000!null 0 R
.%liverange 0 B15 43:86
.%liverange 0 ~B15 39:42
.%var l0000!rx_thd_freelist 0 R
.%liverange 0 B4 7:7 11:11 15:15 17:86
.%var l0000!rbuf_elem_done 0 R
.%liverange 0 B14 22:86
.%var l0000!rbuf_base 0 R
.%liverange 0 B3 21:86
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 87:87
.%liverange 0 $R1 87:87
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:38
.%liverange 0 ~$W0 39:75 86:86
.%liverange 0 $R0 0:86
.%var l0000!rxconfigdata 0 R
.%liverange 0 B13 26:26
.%liverange 0 A2 27:86
.%var l0000!ring 0 R
.%liverange 0 A1 18:86
.%var l0000!t0 0 R
.%liverange 0 B2 20:86
.%var l0000!sram_channel_number 0 R
.%liverange 0 A0 19:86
.%var l0000!cur_ctx 0 R
.%liverange 0 A9 4:86
.%var l0000!cur_me 0 R
.%liverange 0 A8 3:86
.%var l0000!dram_sig 1 R
.%liverange 0 D2 39:71 73:86
.%var l0000!sram_sig 1 R
.%liverange 0 G1 46:66 74:76
.%var l0000!scratch_sig 1 R
.%liverange 0 G1 35:35 83:86
.%var l0000!inter_me_sig 1 R
.%liverange 0 G15 0:36
.%var l0000!same_me_sig 1 R
.%liverange 0 G14 37:42 44:86
.%var l0000!rx_sig 1 R
.%liverange 0 G1 39:42
.%scope end
.0 FC044C0000 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 48 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg l0000!cur_me l0000!cur_ctx
	.%line 49 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg l0000!sram_channel_number l0000!t0
	.%line 50 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg l0000!ring
	.%line 51 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg l0000!rxconfigdata
	.%line 52 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg $l0000!transferreg00 $l0000!transferreg01
	.%line 53 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg l0000!rbuf_base l0000!rbuf_elem_done l0000!rx_thd_freelist
	.%line 54 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg l0000!null l0000!elem l0000!bytecnt l0000!rx_port_num
	.%line 56 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg $l0000!sr0
	.%line 57 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg $l0000!ring_data
	.%line 58 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.reg @l0000!sramdescbase @l0000!drampacketbase @l0000!half_duplex
	.%line 60 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.sig l0000!rx_sig l0000!same_me_sig l0000!inter_me_sig
	.%line 61 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.sig l0000!scratch_sig l0000!sram_sig l0000!dram_sig
	.%line 63 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.xfer_order $l0000!transferreg00 $l0000!transferreg01
	.%line 65 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.set $l0000!transferreg00
	.%line 67 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.set_sig l0000!inter_me_sig
	.%line 69 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.addr l0000!same_me_sig 14
	.%line 70 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.addr l0000!inter_me_sig 15
	.%line 76 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.begin
	.%line 77 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		.reg l0001!temp
	.%line 78 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 1
		local_csr_rd[active_ctx_sts]
.1 F000000B00 common_code
	.%line 79 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 0
		immed[l0001!temp, 0]
.2 843080093F common_code
	.%line 80 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		alu_shf[l0000!cur_me, 0x1f, and, l0001!temp, >>3]
.3 A400900B07 common_code
	.%line 81 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		alu[l0000!cur_ctx, 0x7, and, l0001!temp]
.4 A0700C0008 common_code
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
	.end
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		.if (cur_me == 0)
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		alu[--,--,b,l0000!cur_me]
.5 D802000101 common_code
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0 8
		bne[l000_01#]
.6 F000001330 common_code
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
			immed[l0000!rx_thd_freelist, 0x0030]
.7 D804400018 common_code
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		.elif (cur_me == 1)
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0 17
		br[l000_end#]
.8 AAB00C0408 common_code
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		l000_01#: 
		alu[--,l0000!cur_me,-,1]
.9 D803000101 common_code
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0 12
		bne[l000_02#]
.10 F000001334 common_code
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
			immed[l0000!rx_thd_freelist, 0x0034]
.11 D804400018 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		.elif (cur_me == 2)
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0 17
		br[l000_end#]
.12 AAB00C0808 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		l000_02#: 
		alu[--,l0000!cur_me,-,2]
.13 D804000101 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0 16
		bne[l000_03#]
.14 F000001338 common_code
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
			immed[l0000!rx_thd_freelist, 0x0038]
.15 D804400018 common_code
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		.else
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0 17
		br[l000_end#]
.16 F00000133C common_code
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		l000_03#: 
	.%line 91 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
			immed[l0000!rx_thd_freelist, 0x003c]
.17 F0000C0001 common_code
	.%line 92 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0
		.endif
	.%line 92 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_in_rx.uc" 1 0