line_rate_pl_eg_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:03:20 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:init# 29
:init_common# 7
:l000_01# 7
:l000_end# 7
:me_specific_init_done# 24
:port0# 9
:port1# 13
:port2# 17
:port3# 21
:refcnt_calc_done# 63
:wait_for_assignment# 41
:wait_for_next_ctx_sig# 38
:wait_for_sram_sig# 51
:wake_up_next_thread_after_init# 39
*-- no_destination 0
*l0000!cur_me gpr_b_rel 0B
*l0000!cur_ctx gpr_b_rel 0C
*l0000!ring_num gpr_b_rel 00
*l0000!tbuf_base gpr_b_rel 01
*@l0000!tbuf_element gpr_a_abs 01
*l0000!sram_channel_number gpr_a_rel 02
*l0000!t0 gpr_b_rel 02
*@l0000!sramdescbase gpr_a_abs 11
*@l0000!drampacketbase gpr_a_abs 21
*@l0000!mask_qa gpr_a_abs 31
*l0000!buf_addr gpr_b_rel 03
*l0000!buf_offset gpr_b_rel 04
*l0000!byte_count gpr_a_rel 03
*l0000!base_element_for_port gpr_b_rel 05
*l0000!cur_tbuf_elem gpr_a_rel 04
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x15
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x15
*l0001!temp gpr_b_rel 0D
*l0002!jump_offset gpr_b_rel 0E
*$l0003!scratch_data sram_rel 00 0 both 1 0x0
*$l0004!sram_data sram_rel 00 0 both 1 0x0
;*l0005!refcnt!!2 gpr_a_rel 05
;*l0005!refcnt!!3 gpr_a_rel 05
*l0005!refcnt gpr_a_rel 05
;*l0005!pkt_buf_addr!!2 gpr_a_rel 00
*l0005!pkt_buf_addr gpr_b_rel 06
;*l0005!cur_tbuf_addr!!2 gpr_b_rel 07
;*l0005!cur_tbuf_addr!!3 gpr_b_rel 07
*l0005!cur_tbuf_addr gpr_b_rel 07
;*l0006!msfaddress!!2 gpr_a_rel 06
*l0006!msfaddress gpr_b_rel 08
*l0006!temp gpr_b_rel 09
*l0007!cellcount gpr_b_rel 0A
*l0007!enqueue_data gpr_a_rel 07
*l0000!inter_me_sig signal 0F 0
*l0000!next_ctx_sig signal 0E 0
*l0000!msf_sig signal 01 0
*l0000!dram_sig signal 02 0
*l0000!sram_sig signal 01 0
*l0000!scratch_sig signal 01 0
.%type R
.%type SI
.%scope global
.%var l0007!enqueue_data 0 R
.%liverange 0 A7 75:78
.%liverange 0 ~A7 41:74
.%var l0007!cellcount 0 R
.%liverange 0 B10 76:78
.%liverange 0 ~B10 41:75
.%var l0006!temp 0 R
.%liverange 0 B9 71:78
.%liverange 0 ~B9 41:70
.%var l0006!msfaddress 0 R
.%liverange 0 B8 69:69
.%liverange 0 A6 70:78
.%liverange 0 ~A6 41:68
.%var l0005!cur_tbuf_addr 0 R
.%liverange 0 B7 57:78
.%liverange 0 ~B7 41:56
.%var l0005!pkt_buf_addr 0 R
.%liverange 0 B6 55:55
.%liverange 0 A0 56:78
.%liverange 0 ~A0 41:54
.%var l0005!refcnt 0 R
.%liverange 0 A5 60:78
.%liverange 0 ~A5 41:59
.%var $l0004!sram_data 0 R
.%liverange 0 $W0 79:79
.%liverange 0 $R0 46:78
.%liverange 0 ~$R0 41:41
.%var $l0003!scratch_data 0 R
.%liverange 0 $W0 79:79
.%liverange 0 $R0 42:45
.%liverange 0 ~$R0 41:41
.%var l0002!jump_offset 0 R
.%liverange 0 B14 8:11 13:15 17:19 21:78
.%var l0001!temp 0 R
.%liverange 0 B13 2:11 13:15 17:19 21:78
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 73:78
.%liverange 0 ~$W1 41:72
.%liverange 0 $R1 79:79
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 72:78
.%liverange 0 ~$W0 41:71
.%liverange 0 $R0 79:79
.%var l0000!cur_tbuf_elem 0 R
.%liverange 0 A4 47:78
.%liverange 0 ~A4 41:46
.%var l0000!base_element_for_port 0 R
.%liverange 0 B5 11:11 15:15 19:19 23:78
.%var l0000!byte_count 0 R
.%liverange 0 A3 54:78
.%liverange 0 ~A3 41:53
.%var l0000!buf_offset 0 R
.%liverange 0 B4 53:78
.%liverange 0 ~B4 41:52
.%var l0000!buf_addr 0 R
.%liverange 0 B3 45:78
.%liverange 0 ~B3 41:44
.%var @l0000!mask_qa 0 R
.%liverange 0 @A49 0:78
.%var @l0000!drampacketbase 0 R
.%liverange 0 @A33 0:78
.%var @l0000!sramdescbase 0 R
.%liverange 0 @A17 0:78
.%var l0000!t0 0 R
.%liverange 0 B2 27:78
.%var l0000!sram_channel_number 0 R
.%liverange 0 A2 26:78
.%var @l0000!tbuf_element 0 R
.%liverange 0 @A1 0:78
.%var l0000!tbuf_base 0 R
.%liverange 0 B1 25:78
.%var l0000!ring_num 0 R
.%liverange 0 B0 10:11 14:15 18:19 22:78
.%var l0000!cur_ctx 0 R
.%liverange 0 B12 4:11 13:15 17:19 21:78
.%var l0000!cur_me 0 R
.%liverange 0 B11 3:11 13:15 17:19 21:78
.%var l0000!inter_me_sig 1 R
.%liverange 0 G15 36:37
.%var l0000!next_ctx_sig 1 R
.%liverange 0 G14 38:39
.%var l0000!msf_sig 1 R
.%liverange 0 G1 74:74
.%var l0000!dram_sig 1 R
.%liverange 0 D2 67:68
.%var l0000!sram_sig 1 R
.%liverange 0 G1 46:53
.%var l0000!scratch_sig 1 R
.%liverange 0 G1 42:42
.%scope end
.0 FC044C0000 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 47 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.reg l0000!cur_me l0000!cur_ctx
	.%line 48 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.reg l0000!ring_num
	.%line 49 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.reg l0000!tbuf_base @l0000!tbuf_element
	.%line 50 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.reg l0000!sram_channel_number l0000!t0
	.%line 51 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.reg @l0000!sramdescbase @l0000!drampacketbase @l0000!mask_qa
	.%line 52 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.reg l0000!buf_addr l0000!buf_offset l0000!byte_count
	.%line 53 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.reg l0000!base_element_for_port l0000!cur_tbuf_elem
	.%line 54 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 56 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.sig l0000!scratch_sig l0000!sram_sig l0000!dram_sig l0000!msf_sig
	.%line 57 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.sig l0000!next_ctx_sig l0000!inter_me_sig
	.%line 59 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.xfer_order $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 61 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.addr l0000!next_ctx_sig 14
	.%line 62 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.addr l0000!inter_me_sig 15
	.%line 68 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.begin
	.%line 69 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		.reg l0001!temp
	.%line 70 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 1
		local_csr_rd[active_ctx_sts]
.1 F000003700 common_code
	.%line 71 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 0
		immed[l0001!temp, 0]
.2 9430B0353F common_code
	.%line 72 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		alu_shf[l0000!cur_me, 0x1f, and, l0001!temp, >>3]
.3 B400C03707 common_code
	.%line 73 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		alu[l0000!cur_ctx, 0x7, and, l0001!temp]
.4 AAF0002F04 common_code
	.%line 74 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.end
	.%line 76 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		.if (cur_me > 4)
	.%line 76 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		alu[--,l0000!cur_me,-,4]
.5 D801C0010A common_code
	.%line 76 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0 7
		ble[l000_01#]
.6 E000010000 common_code
	.%line 77 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
			ctx_arb[kill], any
.7 91E0E02E00 common_code
	.%line 78 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		.endif
	.%line 81 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.local l0002!jump_offset
	.%line 78 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		l000_01#: 
		l000_end#: 
	.%line 80 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	init_common#:
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		alu_shf[l0002!jump_offset, --, b, l0000!cur_me, <<2]
.8 E800003B09 common_code
	.%line 83 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0 9 B14
		jump[l0002!jump_offset, port0#], targets[port0#, port1#, port2#, port3#]
.9 91E0008200 common_code
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	.endlocal
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	port0#:
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		alu_shf[l0000!ring_num, --, b, 0, <<2]
.10 F000001700 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		immed[l0000!base_element_for_port, 0]
.11 D806000018 common_code
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0 24
		br[me_specific_init_done#]
.12 F0000C0300 common_code
	.%line 93 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	; The following uwords are unreachable and have been commented out
	; 	nop
	; End commenting out unreachable code
	.%line 93 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	nop ; inserted to restore spacing between jump targets
.13 91E0008600 common_code
	.%line 92 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
	port1#:
	.%line 93 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		alu_shf[l0000!ring_num, --, b, 1, <<2]
.14 F000001710 common_code
	.%line 94 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0
		immed[l0000!base_element_for_port, 16]
.15 D806000018 common_code
	.%line 95 "C:\phase9rel\diag\test_suites\microcode\line_rate_pl\line_rate_pl_eg_tx.uc" 1 0 24