📄 common_uc.h
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/* common_uc.h
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, May 8, 2002
* revisions:
*
*
* --------------------------------------------------------------------------
*/
#ifndef COMMON_UC_H
#define COMMON_UC_H
//#define MSF_WORKAROUND
//#define WORKBENCH_SIM
// **************************************************
// MSF Registers
// **************************************************
#define MSF_RX_CONTROL 0x0000
#define MSF_TX_CONTROL 0x0004
#define CSIX_TYPE_MAP 0x0010
#define HWM_CONTROL 0x0024
#define RX_THREAD_FREELIST_0 0x0030
#define RX_THREAD_FREELIST_1 0x0034
#define RX_THREAD_FREELIST_2 0x0038
#define RX_THREAD_FREELIST_3 0x003C
#define RBUF_ELEMENT_DONE 0x0044
#define RX_THREAD_FREELIST_TIMEOUT_0 0x0050
#define RX_THREAD_FREELIST_TIMEOUT_1 0x0054
#define RX_THREAD_FREELIST_TIMEOUT_2 0x0058
#define RX_THREAD_FREELIST_TIMEOUT_3 0x005C
#define TX_SEQUENCE_0 0x0060
#define TX_SEQUENCE_1 0x0064
#define TX_SEQUENCE_2 0x0068
#define TX_SEQUENCE_3 0x006C
#define RX_UP_CONTROL_0 0x0080
#define RX_UP_CONTROL_1 0x0084
#define RX_UP_CONTROL_2 0x0088
#define RX_UP_CONTROL_3 0x008C
#define TX_UP_CONTROL_0 0x0090
#define TX_UP_CONTROL_1 0x0094
#define TX_UP_CONTROL_2 0x0098
#define TX_UP_CONTROL_3 0x009C
#define FCIFIFO 0x0100 // ( / 0x0100 - 0x013C)
#define FCEFIFO 0x0140
#define TBUF_ELEMENT_CONTROL_V 0x1800 // ( / 0x1800 - 0x1FFC)
#define RBUF_TBUF 0x2000 // (0 to 127 / 0x4000 - 0x5FFF)
//*******************************************************************************
#define MSF_SINGLE_PHY 0
#define MSF_MULTIPLE_PHY 1
#define MSF_WIDTH_1x32 0
#define MSF_WIDTH_2x16 1
#define MSF_WIDTH_4x8 2
#define MSF_WIDTH_1x16_2x8 3
#define MSF_POS_UTOPIA 0
#define MSF_CSIX 1
#define MSF_ELEMENTSIZE_256 2
#define MSF_ELEMENTSIZE_128 1
#define MSF_ELEMENTSIZE_64 0
#define MSF_PARITY_EVEN 3
#define MSF_PARITY_ODD 2
#define MSF_PARITY_NONE 0
#define MSF_HEC_ENABLE 1
#define MSF_HEC_DISABLE 0
#define MSF_CSIX_DISCARD 0
#define MSF_CSIX_RBUF_CONTROL 1
#define MSF_CSIX_RBUF_DATA 2
#define MSF_CSIX_FCEFIFO 3
#define MSF_POS2 0
#define MSF_POS3 1
#define RBUF_SIZE 0x2000
// UP_Control Settings
#define UP_CTRL_DRTIME 1 // 0=1cycle, 1=2cycles
#define UP_CTRL_CELLSIZE (0 << 1) // 0=52 bytes, 1=56 bytes
#define UP_CTRL_PARITY (MSF_PARITY_EVEN << 2)
#define UP_CTRL_PARITY_ODD (MSF_PARITY_ODD << 2)
#define UP_CTRL_CP_MODE (1 << 4) // 1=packet mode, 0=cell mode
#define UP_CTRL_PP_MODE (MSF_POS2 << 5)
#define UP_CTRL_PP_MODE_PLONE (MSF_POS3 << 5)
#define CSIX_UNICAST 1
#define CSIX_FLOWCONTROL 6
#define BIT_SHF_UNICAST (CSIX_UNICAST * 2)
#define BIT_SHF_FLOWCONTROL (CSIX_FLOWCONTROL * 2)
#define CSIX_BASE_HDR_LEN 2 // CSIX Base Header Length = 2 bytes
#define CSIX_TAIL_LEN 1 // CSIX Tail Length = 1 byte
//*******************************************************************************
#define MASK_1BIT 0x1
#define MASK_2BIT 0x3
#define MASK_3BIT 0x7
#define MASK_4BIT 0xF
#define MASK_5BIT 0x1F
#define MASK_6BIT 0x3F
#define MASK_7BIT 0x7F
#define MASK_8BIT 0xFF
#define MASK_16BIT 0xFFFF
#define SHIFT_1 1
#define SHIFT_2 2
#define SHIFT_3 3
#define SHIFT_4 4
#define SHIFT_5 5
#define SHIFT_6 6
#define SHIFT_7 7
#define SHIFT_8 8
#define SHIFT_9 9
#define SHIFT_10 10
#define SHIFT_11 11
#define SHIFT_12 12
#define SHIFT_13 13
#define SHIFT_14 14
#define SHIFT_15 15
#define SHIFT_16 16
#define SHIFT_17 17
#define SHIFT_18 18
#define SHIFT_19 19
#define SHIFT_20 20
#define SHIFT_21 21
#define SHIFT_22 22
#define SHIFT_23 23
#define SHIFT_24 24
#define SHIFT_25 25
#define SHIFT_26 26
#define SHIFT_27 27
#define SHIFT_28 28
#define SHIFT_29 29
#define SHIFT_30 30
#define SHIFT_31 31
#define PACKET_SENT 0x1010
#define PACKET_RECEIVED 0x2020
#define TEST_COMPLETE 0xBABE
#define ERROR_PATTERN 0xF0F0
#define INCORRECT_TYPE 0xF1F1
#define INCORRECT_SIZE 0xF2F2
#define NOT_SENT 0xF3F3
#define NOT_RECEIVED 0xF4F4
#define SLAVE_MAILBOX0_NO_SIG 0xF5F5
#define SLAVE_MAILBOX1_NO_SIG 0xF6F6
#define INIT_ERROR 0xF7F7
#define INIT_COMPLETE 0xF8F8
#define NOT_COMPLETE 0xF9F9
#define RECEIVE_ERROR 0xFAFA
#define SEQUENCE_ERROR 0xFBFB
#define PCI_LOCAL_CSR_BASE 0x7000000
#define MAILBOX0_OFFSET 0x50
#define MAILBOX1_OFFSET 0x54
#define MAILBOX2_OFFSET 0x58
#define MAILBOX3_OFFSET 0x5c
#define RING_0 0
#define RING_1 1
#define RING_2 2
#define RING_3 3
#define RING_4 4
#define RING_5 5
#define RING_6 6
#define RING_7 7
#define RINGSIZE_128 0
#define RINGSIZE_256 1
#define RINGSIZE_512 2
#define RINGSIZE_1024 3
#define RINGBASE_128_0 0x0
#define RINGBASE_128_1 0x1
#define RINGBASE_128_2 0x2
#define RINGBASE_128_3 0x3
#define RINGBASE_128_4 0x4
#define RINGBASE_128_5 0x5
#define RINGBASE_128_6 0x6
#define RINGBASE_128_7 0x7
#define RINGBASE_128_8 0x8
#define RINGBASE_128_9 0x9
#define RINGBASE_128_10 0xA
#define RINGBASE_128_11 0xB
#define RINGBASE_128_12 0xC
#define RINGBASE_128_13 0xD
#define RINGBASE_128_14 0xE
#define RINGBASE_128_15 0xF
#define RINGBASE_128_16 0x10
#define RINGBASE_128_17 0x11
#define RINGBASE_128_18 0x12
#define RINGBASE_128_19 0x13
#define RINGBASE_128_20 0x14
#define RINGBASE_128_21 0x15
#define RINGBASE_128_22 0x16
#define RINGBASE_128_23 0x17
#define RINGBASE_128_24 0x18
#define RINGBASE_128_25 0x19
#define RINGBASE_128_26 0x1A
#define RINGBASE_128_27 0x1B
#define RINGBASE_128_28 0x1C
#define RINGBASE_128_29 0x1D
#define RINGBASE_128_30 0x1E
#define RINGBASE_128_31 0x1F
#define RINGBASE_256_0 RINGBASE_128_0
#define RINGBASE_256_1 RINGBASE_128_2
#define RINGBASE_256_2 RINGBASE_128_4
#define RINGBASE_256_3 RINGBASE_128_6
#define RINGBASE_256_4 RINGBASE_128_8
#define RINGBASE_256_5 RINGBASE_128_10
#define RINGBASE_256_6 RINGBASE_128_12
#define RINGBASE_256_7 RINGBASE_128_14
#define RINGBASE_256_8 RINGBASE_128_16
#define RINGBASE_256_9 RINGBASE_128_18
#define RINGBASE_256_10 RINGBASE_128_20
#define RINGBASE_256_11 RINGBASE_128_22
#define RINGBASE_256_12 RINGBASE_128_24
#define RINGBASE_256_13 RINGBASE_128_26
#define RINGBASE_256_14 RINGBASE_128_28
#define RINGBASE_256_15 RINGBASE_128_30
#define RINGBASE_512_0 RINGBASE_256_0
#define RINGBASE_512_1 RINGBASE_256_2
#define RINGBASE_512_2 RINGBASE_256_4
#define RINGBASE_512_3 RINGBASE_256_6
#define RINGBASE_512_4 RINGBASE_256_8
#define RINGBASE_512_5 RINGBASE_256_10
#define RINGBASE_512_6 RINGBASE_256_12
#define RINGBASE_512_7 RINGBASE_256_14
#define RINGBASE_1024_0 RINGBASE_512_0
#define RINGBASE_1024_1 RINGBASE_512_2
#define RINGBASE_1024_2 RINGBASE_512_4
#define RINGBASE_1024_3 RINGBASE_512_6
#define SRAM_CHANNEL_NUMBER_FIELD 30
#define SRAM_Q_ARRAY_NUMBER_FIELD 24
#define CHAN_NUMBER 1
#define Q_NUMBER 0
#define MOP 0 // 00
#define NOSOP_EOP 1 // 01
#define SOP_NOEOP 2 // 10
#define SOP_EOP 3 // 11
#define PREPEND_LENGTH 8
#ifdef WORKBENCH_SIM
#define FREELIST_SIZE 128
#else
#define FREELIST_SIZE 4096
#endif
#define FREELIST_TIMEOUT_VAL 256
#endif // #ifdef COMMON_UC_H⌨️ 快捷键说明
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