sys_loopback_pl_3_eg_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:00:37 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:cont_comp_tbuf_tx_sequnce# 87
:init# 2
:init_msf# 44
:l000_01# 28
:l000_02# 33
:l000_03# 38
:l000_end# 40
:l001_01# 122
:l001_end# 123
:l002_01# 110
:l002_end# 110
:l003_01# 114
:l003_end# 114
:msf_init_done# 73
:next_burst# 74
:next_packet# 76
:read_tx_sequence_loop# 80
:wait_for_xscale# 117
*-- no_destination 0
*l0000!cur_me gpr_b_rel 05
;*l0000!msfaddress!!2 gpr_b_rel 06
;*l0000!msfaddress!!3 gpr_b_rel 06
;*l0000!msfaddress!!4 gpr_b_rel 06
;*l0000!msfaddress!!5 gpr_b_rel 06
;*l0000!msfaddress!!6 gpr_b_rel 06
;*l0000!msfaddress!!7 gpr_a_rel 05
;*l0000!msfaddress!!8 gpr_a_rel 05
*l0000!msfaddress gpr_b_rel 06
*l0000!txsequenceaddr gpr_b_rel 00
*l0000!pkt_in_one_burst gpr_a_rel 00
*l0000!pkt_in_cur_burst gpr_b_rel 01
*l0000!total_loop gpr_a_rel 01
*l0000!cur_loop gpr_b_rel 02
;*l0000!future_count_value!!2 gpr_b_rel 07
*l0000!future_count_value gpr_a_rel 02
*l0000!future_count_incr gpr_b_rel 03
*l0000!byte_count gpr_a_rel 03
*$l0000!misc_ctrl_val sram_rel 00 0 both 1 0x0
;*l0000!txconfigdata0!!2 gpr_a_rel 06
;*l0000!txconfigdata0!!3 gpr_a_rel 06
*l0000!txconfigdata0 gpr_a_rel 06
*$l0000!txconfigdata0 sram_rel 00 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x22
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x22
;*l0000!tbuf_element!!2 gpr_b_rel 08
*l0000!tbuf_element gpr_a_rel 04
*l0000!base_element_for_port gpr_b_rel 04
*l0001!temp gpr_b_rel 02
*l0002!temp_scratch_addr gpr_b_rel 03
*$l0002!temp_scratch_data sram_rel 00 0 both 1 0x0
*l0003!temp_scratch_addr gpr_b_rel 00
*$l0003!temp_scratch_data sram_rel 00 0 both 1 0x0
*l0004!temp_scratch_addr gpr_b_rel 01
*$l0004!temp_scratch_data sram_rel 00 0 both 1 0x0
;*l0005!temp!!2 gpr_b_rel 09
;*l0005!temp!!3 gpr_b_rel 09
*l0005!temp gpr_b_rel 09
;*l0006!result!!2 gpr_b_rel 0A
*l0006!result gpr_a_rel 07
*l0006!tmp_val gpr_b_rel 0B
*l0006!tmp_tbuf gpr_b_rel 0C
*$l0006!txsequencedata sram_rel 00 0 both 1 0x0
;*l0007!debug_addr!!2 gpr_b_rel 0D
*l0007!debug_addr gpr_a_rel 08
*$l0007!debug_xfer_reg sram_rel 00 0 both 1 0x0
*l0008!temp gpr_b_rel 0E
*l0008!cur_tbuf_elem gpr_b_rel 0F
;*l0009!temp_scratch_addr!!2 gpr_b_rel 07
*l0009!temp_scratch_addr gpr_a_rel 09
*$l0009!temp_scratch_data sram_rel 00 0 both 1 0x0
*l0009!scratch_sig signal 02 0
*l0007!debug_sig signal 02 0
*l0004!scratch_sig signal 01 0
*l0003!scratch_sig signal 01 0
*l0002!scratch_sig signal 01 0
*l0000!cap_sig signal 01 0
*l0000!inter_me_sig signal 0F 0
*l0000!future_count_sig signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!8 signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var $l0009!temp_scratch_data 0 R
.%liverange 0 $W0 117:121
.%liverange 0 ~$W0 76:92
.%liverange 0 $R0 118:121
.%liverange 0 ~$R0 76:80 117:117
.%var l0009!temp_scratch_addr 0 R
.%liverange 0 A9 115:115
.%liverange 0 B7 116:121
.%liverange 0 ~B7 76:77
.%var l0008!cur_tbuf_elem 0 R
.%liverange 0 B15 95:123
.%liverange 0 ~B15 76:94
.%var l0008!temp 0 R
.%liverange 0 B14 98:123
.%liverange 0 ~B14 76:97
.%var $l0007!debug_xfer_reg 0 R
.%liverange 0 $W0 93:98
.%liverange 0 $R0 124:124
.%var l0007!debug_addr 0 R
.%liverange 0 A8 91:91
.%liverange 0 B13 92:123
.%liverange 0 ~B13 76:90
.%var $l0006!txsequencedata 0 R
.%liverange 0 $W0 124:124
.%liverange 0 $R0 81:116 122:123
.%liverange 0 ~$R0 76:80 117:117
.%var l0006!tmp_tbuf 0 R
.%liverange 0 B12 86:123
.%liverange 0 ~B12 76:85
.%var l0006!tmp_val 0 R
.%liverange 0 B11 83:123
.%liverange 0 ~B11 76:82
.%var l0006!result 0 R
.%liverange 0 A7 82:87
.%liverange 0 B10 88:123
.%liverange 0 ~B10 76:81
.%var l0005!temp 0 R
.%liverange 0 B9 65:75
.%liverange 0 ~B9 76:123
.%var $l0004!temp_scratch_data 0 R
.%liverange 0 $W0 124:124
.%liverange 0 $R0 16:73
.%liverange 0 ~$R0 76:80
.%var l0004!temp_scratch_addr 0 R
.%liverange 0 B1 15:17
.%var $l0003!temp_scratch_data 0 R
.%liverange 0 $W0 124:124
.%liverange 0 $R0 13:15
.%var l0003!temp_scratch_addr 0 R
.%liverange 0 B0 12:26 28:31 33:36 38:39
.%var $l0002!temp_scratch_data 0 R
.%liverange 0 $W0 124:124
.%liverange 0 $R0 10:12
.%var l0002!temp_scratch_addr 0 R
.%liverange 0 B3 9:10
.%var l0001!temp 0 R
.%liverange 0 B2 4:7
.%var l0000!base_element_for_port 0 R
.%liverange 0 B4 26:27 31:32 36:37 39:123
.%var l0000!tbuf_element 0 R
.%liverange 0 A4 6:102 104:123
.%liverange 0 B8 103:103
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 100:123
.%liverange 0 ~$W1 76:99
.%liverange 0 $R1 124:124
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 99:116 122:123
.%liverange 0 ~$W0 76:92
.%liverange 0 $R0 124:124
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W0 48:75
.%liverange 0 ~$W0 76:92
.%liverange 0 $R0 124:124
.%var l0000!txconfigdata0 0 R
.%liverange 0 A6 46:75
.%liverange 0 ~A6 76:123
.%var $l0000!misc_ctrl_val 0 R
.%liverange 0 $W0 124:124
.%liverange 0 $R0 74:75
.%liverange 0 ~$R0 76:80
.%var l0000!byte_count 0 R
.%liverange 0 A3 7:123
.%var l0000!future_count_incr 0 R
.%liverange 0 B3 11:123
.%var l0000!future_count_value 0 R
.%liverange 0 A2 19:77 79:123
.%liverange 0 B7 78:78
.%var l0000!cur_loop 0 R
.%liverange 0 B2 8:123
.%var l0000!total_loop 0 R
.%liverange 0 A1 14:123
.%var l0000!pkt_in_cur_burst 0 R
.%liverange 0 B1 18:123
.%var l0000!pkt_in_one_burst 0 R
.%liverange 0 A0 17:123
.%var l0000!txsequenceaddr 0 R
.%liverange 0 B0 27:27 32:32 37:37 40:123
.%var l0000!msfaddress 0 R
.%liverange 0 B6 45:75
.%liverange 0 ~B6 76:95
.%liverange 0 A5 96:123
.%liverange 0 ~A5 76:95
.%var l0000!cur_me 0 R
.%liverange 0 B5 5:123
.%var l0009!scratch_sig 1 R
.%liverange 0 D2 118:119
.%var l0007!debug_sig 1 R
.%liverange 0 G2 94:94
.%var l0004!scratch_sig 1 R
.%liverange 0 G1 16:16
.%var l0003!scratch_sig 1 R
.%liverange 0 G1 13:13
.%var l0002!scratch_sig 1 R
.%liverange 0 G1 10:10
.%var l0000!cap_sig 1 R
.%liverange 0 G1 74:74
.%var l0000!inter_me_sig 1 R
.%liverange 0 G15 0:0 2:43
.%var l0000!future_count_sig 1 R
.%liverange 0 G1 94:101
.%var l0000!msf_sig 1 R
.%liverange 0 G1 49:49 53:53 55:55 57:57 59:59 64:64 81:81 102:111 122:123
.%scope end
.0 D800800010 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg l0000!cur_me
	.%line 83 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg l0000!msfaddress l0000!txsequenceaddr
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg l0000!pkt_in_one_burst l0000!pkt_in_cur_burst
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg l0000!total_loop l0000!cur_loop
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg l0000!future_count_value l0000!future_count_incr
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg l0000!byte_count
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg $l0000!misc_ctrl_val
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg l0000!txconfigdata0
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg $l0000!txconfigdata0
	.%line 91 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 92 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.reg l0000!tbuf_element l0000!base_element_for_port
	.%line 93 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.sig l0000!msf_sig l0000!future_count_sig l0000!inter_me_sig l0000!cap_sig
	.%line 95 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0
	.xfer_order $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 97 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_pl_3\sys_loopback_pl_3_eg_tx.uc" 1 0