📄 me_context_test.list
字号:
+version: 10/31/2000
+switches:
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Mon Mar 01 17:16:59 2004
.cpu_version 0x00000002 1 255
.%num_contexts 8
.%local_mem0_mode rel
.%local_mem1_mode rel
.%init_nn_mode neighbor
.%legacy xfer on
:check_ctx0_ctx3# 40
:check_ctx4_ctx7# 60
:continue# 114
:ctx0_ctx3_error# 76
:ctx4_ctx7_error# 76
:ctx_sleep_test# 81
:done_init# 28
:end# 120
:handle_ctx0_branch# 110
:inactive_test_complete# 81
:me_offset_obtain# 12
:sleep# 99
:sleep_state_fail# 116
*-- no_destination 0
;*l0000!scratch_offset!!2 gpr_a_rel 00
*l0000!scratch_offset gpr_a_rel 00
*@l0000!counter gpr_a_abs 01
;*l0000!ctx_en_bits!!2 gpr_a_rel 02
;*l0000!ctx_en_bits!!3 gpr_a_rel 02
*l0000!ctx_en_bits gpr_a_rel 02
;*l0000!next_ctx!!2 gpr_b_rel 00
;*l0000!next_ctx!!3 gpr_b_rel 00
;*l0000!next_ctx!!4 gpr_a_rel 03
*l0000!next_ctx gpr_b_rel 00
;*l0000!thd_to_inter_thread!!2 gpr_b_rel 03
*l0000!thd_to_inter_thread gpr_b_rel 03
;*l0000!temp!!2 gpr_b_rel 04
*l0000!temp gpr_b_rel 04
;*l0000!me!!2 gpr_b_rel 01
*l0000!me gpr_b_rel 01
;*l0000!me_offset!!2 gpr_b_rel 02
*l0000!me_offset gpr_b_rel 02
;*l0000!inter_thread_reg!!2 gpr_b_rel 05
*l0000!inter_thread_reg gpr_b_rel 05
*$l0000!status0 sram_rel 00 0 both 2 0x2
*$l0000!status1 sram_rel 01 0 both 1 0x2
*l0000!signal1 signal 01 0
*l0000!scratch_write signal 01 0
*l0000!scratch_write!!5 signal 01 0
*l0000!scratch_write!!4 signal 01 0
*l0000!scratch_write!!3 signal 01 0
*l0000!scratch_write!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var $l0000!status1 0 R
.%liverange 0 $W1 57:59 78:80 96:98 103:115 118:124
.%liverange 0 ~$W1 81:95 99:102 116:117
.%liverange 0 $R1 126:126
.%var $l0000!status0 0 R
.%liverange 0 $W0 56:59 77:80 95:98 102:115 117:124
.%liverange 0 ~$W0 81:94 99:101 116:116
.%liverange 0 $R0 126:126
.%var l0000!inter_thread_reg 0 R
.%liverange 0 B5 90:98
.%liverange 0 ~B5 120:124
.%var l0000!me_offset 0 R
.%liverange 0 B2 9:124
.%var l0000!me 0 R
.%liverange 0 B1 7:124
.%var l0000!temp 0 R
.%liverange 0 B4 107:109 113:115
.%liverange 0 ~B4 120:124
.%var l0000!thd_to_inter_thread 0 R
.%liverange 0 B3 109:109 114:115
.%liverange 0 ~B3 120:124
.%var l0000!next_ctx 0 R
.%liverange 0 B0 3:107 110:113 116:119
.%liverange 0 ~B0 114:115 120:124
.%liverange 0 A3 108:109
.%liverange 0 ~A3 114:115 120:124
.%var l0000!ctx_en_bits 0 R
.%liverange 0 A2 16:27 43:59 63:75
.%liverange 0 ~A2 28:42 60:62 76:124
.%var @l0000!counter 0 R
.%liverange 0 @A1 0:125
.%var l0000!scratch_offset 0 R
.%liverange 0 A0 1:124
.%var l0000!signal1 1 R
.%liverange 0 G1 93:93 100:100
.%var l0000!scratch_write 1 R
.%liverange 0 G1 58:59 79:80 97:98 104:105 119:120
.%scope end
.0 F0000C0000 common_code
.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
.%line 42 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
.reg l0000!scratch_offset @l0000!counter l0000!ctx_en_bits l0000!next_ctx l0000!thd_to_inter_thread l0000!temp l0000!me l0000!me_offset l0000!inter_thread_reg
.%line 43 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
.reg $l0000!status0 $l0000!status1
.%line 44 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
.xfer_order $l0000!status0 $l0000!status1
.%line 45 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
.sig l0000!scratch_write l0000!signal1
.%line 46 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
.addr l0000!signal1 0x1
.%line 48 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
immed[l0000!scratch_offset, 0]
.1 FC044C0000 common_code
.%line 50 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 1
local_csr_rd[active_ctx_sts]
.2 F000000300 common_code
.%line 51 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 0
immed[l0000!next_ctx, 0]
.3 B440000307 common_code
.%line 52 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[l0000!next_ctx, l0000!next_ctx, and, 0x7]
.4 B0C0000301 common_code
.%line 53 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[l0000!next_ctx, l0000!next_ctx, +, 1]
.5 FC044C0000 common_code
.%line 56 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 1
local_csr_rd[active_ctx_sts]
.6 F000000700 common_code
.%line 57 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 0
immed[l0000!me, 0]
.7 943010053F common_code
.%line 58 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu_shf[l0000!me, 0x1f, and, l0000!me, >>3]
.8 B400200703 common_code
.%line 59 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[l0000!me_offset, 0x3, and, l0000!me]
.9 AAF0000703 common_code
.%line 60 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[--, l0000!me, -, 0x3]
.10 D80300010A common_code
.%line 61 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0 12
ble[me_offset_obtain#]
.11 BA40200B04 common_code
.%line 63 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[l0000!me_offset, l0000!me_offset, or, 0x4]
.12 91D0200A00 common_code
.%line 65 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
me_offset_obtain#:
.%line 66 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu_shf[l0000!me_offset, --, b, l0000!me_offset, <<3]
.13 D807000011 common_code
.%line 80 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0 28
br!=ctx[0, done_init#]
.14 F0000C0081 common_code
.%line 81 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
immed[@l0000!counter, 0]
.15 F00F0C0002 common_code
.%line 82 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
immed[l0000!ctx_en_bits, 61440]
.16 FC01AC0002 common_code
.%line 83 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
local_csr_wr[ctx_enables, l0000!ctx_en_bits]
.17 F0000C0300 common_code
.%line 84 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
.macro_ref multi_nop(10)
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.18 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.19 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.20 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.21 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.22 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.23 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.24 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.25 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.26 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.27 E000000001 common_code
.%line 39 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
.end_macro_ref multi_nop
.%line 85 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
ctx_arb[voluntary]
.28 A0881C0481 common_code
.%line 87 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
done_init#:
.%line 90 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[@l0000!counter, @l0000!counter, +, 1]
.29 E000000001 common_code
.%line 91 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
ctx_arb[voluntary]
.30 A0881C0481 common_code
.%line 92 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[@l0000!counter, @l0000!counter, +, 1]
.31 E000000001 common_code
.%line 93 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
ctx_arb[voluntary]
.32 A0881C0481 common_code
.%line 94 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[@l0000!counter, @l0000!counter, +, 1]
.33 E000000001 common_code
.%line 95 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
ctx_arb[voluntary]
.34 A0881C0481 common_code
.%line 96 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[@l0000!counter, @l0000!counter, +, 1]
.35 E000000001 common_code
.%line 97 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
ctx_arb[voluntary]
.36 D80A000010 common_code
.%line 99 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0 40
br=ctx[0, check_ctx0_ctx3#]
.37 D80F010010 common_code
.%line 100 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0 60
br=ctx[4, check_ctx4_ctx7#]
.38 E000000001 common_code
.%line 101 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
ctx_arb[voluntary]
.39 D814400018 common_code
.%line 102 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0 81
br[inactive_test_complete#]
.40 AAB00C8081 common_code
.%line 105 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
check_ctx0_ctx3#:
.%line 106 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
alu[--, @l0000!counter, -, 32]
.41 D813000101 common_code
.%line 108 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0 76
bne[ctx0_ctx3_error#]
.42 F00FFC0002 common_code
.%line 109 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
immed[l0000!ctx_en_bits, 65280]
.43 FC01AC0002 common_code
.%line 110 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
local_csr_wr[ctx_enables, l0000!ctx_en_bits]
.44 F0000C0300 common_code
.%line 111 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
.macro_ref multi_nop(10)
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.45 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.46 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.47 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.48 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.49 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
nop
.50 F0000C0300 common_code
.%line 35 "C:\phase9rel\diag\test_suites\microcode\ME_Context_Test\ME_Context_Test.uc" 1 0
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