me_context_test.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* ME_Context_Test.uc
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXP2400
 *  subsystem: DIAG
 *  author: ccm, Mar 25, 02
 * 
 * --------------------------------------------------------------------------
 */
#include "../../../include/me_xscale_sync.h"

#macro multi_nop(loops)
#define X 0
#while(X < loops)
nop
#define_eval X (X + 1)
#endloop
#undef X
#endm

#define SIGNAL1_BIT 0x1
.reg scratch_offset @counter ctx_en_bits next_ctx thd_to_inter_thread temp me me_offset inter_thread_reg
.reg $status0 $status1
.xfer_order $status0 $status1
.sig scratch_write signal1
.addr signal1 SIGNAL1_BIT

immed[scratch_offset, 0]
// each ctx obtains its own ctx and add 1 to determine the next_ctx to signal
local_csr_rd[active_ctx_sts]
immed[next_ctx, 0]
alu[next_ctx, next_ctx, AND, 0x7]
alu[next_ctx, next_ctx, +, 1]

// calculate me_offset
local_csr_rd[active_ctx_sts]
immed[me, 0]
alu_shf[me, 0x1f, AND, me, >>3]
alu[me_offset, 0x3, AND, me]
alu[--, me, -, 0x3]
ble[me_offset_obtain#]

alu[me_offset, me_offset, OR, 0x4]

me_offset_obtain#:
alu_shf[me_offset, --, B, me_offset, <<3]


// **********************************
// * Test Context In Inactive State *
// **********************************
// Flow:	First ctx0 will disable ctx0-ctx3
//			Then, ctx4-ctx7 will increment the counter
//			till a certain value. Then ctx4 will enable
//			ctx0-ctx3 and disable ctx4-ctx7. Ctx0-ctx3
//			will now increment the counter. Finally,
//			ctx0 will check if the counter has been
//			incremented correctly and enable all contexts.

br!=ctx[0, done_init#]
immed[@counter, 0]
immed[ctx_en_bits, (0xF0<<8)]	// disable ctx 0-3
local_csr_wr[ctx_enables, ctx_en_bits]
multi_nop(10)
ctx_arb[voluntary]

done_init#:
// the below alu and ctx_arb cmds are used to detect any errors
// in ctx not entering the inactive state or not coming out of it
alu[@counter, @counter, +, 1]
ctx_arb[voluntary]
alu[@counter, @counter, +, 1]
ctx_arb[voluntary]
alu[@counter, @counter, +, 1]
ctx_arb[voluntary]
alu[@counter, @counter, +, 1]
ctx_arb[voluntary]

br=ctx[0, check_ctx0_ctx3#]
br=ctx[4, check_ctx4_ctx7#]
ctx_arb[voluntary]
br[inactive_test_complete#]	// ctx0-ctx2 and ctx4-ctx6 branches to test complete


check_ctx0_ctx3#:
alu[--, @counter, -, 32] 	// checks if only 4 ctx were active
							// and the other 4 were inactive
bne[ctx0_ctx3_error#]		// branch if error
immed[ctx_en_bits, (0xFF<<8)] // enable all the ctx
local_csr_wr[ctx_enables, ctx_en_bits]
multi_nop(10)
ctx_arb[voluntary]

// ctx0 write PASS status ($status1 = 0) to scratch
immed[$status0, COMPLETE]
immed[$status1, PASS]
scratch[write, $status0, me_offset, scratch_offset, 2], sig_done[scratch_write]
ctx_arb[scratch_write]
br[inactive_test_complete#]	// ctx0 branches to inactive test complete

check_ctx4_ctx7#:
alu[--, @counter, -, 16]	// checks if only 4 ctx were active
							// and the other 4 were inactive
bne[ctx4_ctx7_error#]		// branch if error
immed[ctx_en_bits, (0xF<<8)]// enable ctx0-3 and disable ctx4-7
local_csr_wr[ctx_enables, ctx_en_bits]
multi_nop(10)
ctx_arb[voluntary]
br[inactive_test_complete#] // ctx4 branches to inactive test complete

ctx0_ctx3_error#:
ctx4_ctx7_error#:
// In an error, the intermediate status is written (@counter)
immed[$status0, COMPLETE]	// indicates test got completed
alu[$status1, --, B, @counter]
scratch[write, $status0, me_offset, scratch_offset, 2], sig_done[scratch_write]
ctx_arb[scratch_write]
br[end#]

inactive_test_complete#:


// *******************************
// * Test Context In Sleep State *
// *******************************

// Flow: 	ctx1-ctx7 wait for inter-thread signal. Ctx0 will
//			check if all ctx1-ctx7 goes to sleep, else return
//			one of the ctx that did not.
//			Then ctx1, writes its status to scratch, then
//			inter-threads ctx2. Ctx2 in turn writes its status
//			to scratch, then inter-threads ctx3. This goes on
//			until ctx7, which checks if ctx0 went to sleep. If
//			ctx0 did not go to sleep then ctx7 returns that ctx0
//			did not go to sleep, else it will inter-thread ctx0.
//			Ctx0 will write the status test completed with a
//			PASS into scratch.
ctx_sleep_test#:
immed[scratch_offset, 64]	// 16 LW, the 1st 16 has been used by inactive test
br!=ctx[0, sleep#]
immed[@counter, 0]
ctx_arb[voluntary]
ctx_arb[voluntary]
ctx_arb[voluntary]

// Check that threads 1-7 went to sleep
alu[@counter, @counter, -, 0]
bne[SLEEP_STATE_FAIL#]

alu_shf[inter_thread_reg, --, B, me, <<7]
alu[inter_thread_reg, inter_thread_reg, +, (SIGNAL1_BIT + (1<<4))]
cap[fast_wr, ALU, interthread_sig]

ctx_arb[signal1]			// ctx0 waits for inter-thread signal from ctx7
immed[@counter, 0xFF]		// used by thd 7 to check if thd 0 went to sleep
immed[$status0, COMPLETE]	// to indicate test completed
immed[$status1, PASS]		// to indicate a PASS
scratch[write, $status0, me_offset, scratch_offset, 2], sig_done[scratch_write]
ctx_arb[scratch_write]
br[end#]

sleep#:	// ctx1-ctx7 branches here to wait for inter-thread signal
ctx_arb[signal1]
alu[@counter, @counter, +, next_ctx]// used by thd 0 to check which thd did not sleep

// each ctx will write its own status, so that in case of an inter-thread failure
// the ctx that failed can be determined
immed[$status0, COMPLETE]		// to indicate test completed
alu[$status1, --, B, next_ctx]
scratch[write, $status0, me_offset, scratch_offset, 2], sig_done[scratch_write]
ctx_arb[scratch_write]

br=ctx[7, handle_ctx0_branch#]
// set temp for inter-threading next ctx
alu_shf[temp, SIGNAL1_BIT, OR, me, <<7]
alu[next_ctx, --, B, next_ctx, <<4]
alu_shf[thd_to_inter_thread, temp, +, next_ctx]
br[continue#]

handle_ctx0_branch#:		// ONLY for ctx7
alu[--, @counter, -, 0xFF]	// Check that thread 0 went to sleep
beq[SLEEP_STATE_FAIL#]
// set temp for inter-threading ctx0
alu_shf[temp, SIGNAL1_BIT, OR, me, <<7]
alu_shf[thd_to_inter_thread, temp, +, 0]


continue#:
cap[fast_wr, ALU, interthread_sig]	// inter-thread according to temp's value
br[end#]


SLEEP_STATE_FAIL#:
// Written when one of the ctx did not go to sleep
immed[$status0, THD_DID_NOT_SLEEP]
alu[$status1, --, B, @counter]		// set to which ctx failed to sleep
scratch[write, $status0, me_offset, scratch_offset, 2], sig_done[scratch_write]
ctx_arb[scratch_write]

end#:
nop
nop
nop
nop
ctx_arb[kill]
nop
nop
nop
nop