pl_media_loopback_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.0.411
+uca_date: Sep  9 2002 00:25:20
+current_date: Thu Feb 06 10:54:26 2003

.cpu_version 0x00000002 0 15

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:addfreelist# 74
:cont_init1# 13
:cont_init2# 35
:cont_rcv# 131
:init_rbuf# 41
:init_value# 0
:is_eop# 130
:l000_01# 106
:l000_end# 106
:no_error# 92
:not_ctx_0# 3
:not_ctx_1# 6
:not_ctx_2# 9
:not_ctx_3# 12
:proc_mop# 112
:proc_nosop_eop# 112
:proc_sop_eop# 104
:proc_sop_noeop# 104
:receivepacket# 89
:rsw# 91
:set_refcnt_overwrite_bit# 118
:store_mpacket# 114
*-- no_destination 0
*$l0000!transferreg00 sram_rel 01 0 both 2 0x4A
*$l0000!transferreg01 sram_rel 02 0 both 1 0x4A
;*l0000!rxthreadlist!!2 gpr_a_rel 08
;*l0000!rxthreadlist!!3 gpr_b_rel 0F
*l0000!rxthreadlist gpr_a_rel 08
*l0000!bytecnt gpr_b_rel 00
*l0000!elem gpr_b_rel 01
*l0000!error gpr_b_rel 0C
*l0000!rx_channel_num gpr_b_rel 02
*l0000!sopeop gpr_a_rel 00
*l0000!total_bytes_rx gpr_a_rel 01
;*l0000!rxconfigdata!!2 gpr_a_rel 02
*l0000!rxconfigdata gpr_b_rel 00
*l0000!rbuf gpr_a_rel 03
*l0000!ring_num gpr_b_rel 06
;*l0000!msfaddress!!2 gpr_b_rel 07
;*l0000!msfaddress!!3 gpr_b_rel 07
;*l0000!msfaddress!!4 gpr_b_rel 07
;*l0000!msfaddress!!5 gpr_b_rel 07
;*l0000!msfaddress!!6 gpr_b_rel 07
*l0000!msfaddress gpr_b_rel 07
*l0000!threadfreelist_addr gpr_b_rel 03
*l0000!elementdone_addr gpr_b_rel 04
*l0000!drampacketbase gpr_a_rel 04
*l0000!sramdescbase gpr_a_rel 05
*l0000!sram_channel_number gpr_b_rel 04
*l0000!t0 gpr_b_rel 05
;*l0000!freebuffer!!2 gpr_b_rel 0A
*l0000!freebuffer gpr_b_rel 0A
;*l0000!rel!!2 gpr_b_rel 0B
*l0000!rel gpr_b_rel 0B
*l0000!pkt_buff_addr gpr_b_rel 06
*$l0000!sr0 sram_rel 00 0 both 1 0x0
*l0001!temp gpr_b_rel 05
*l0001!cur_me gpr_b_rel 01
*l0001!cur_ctx gpr_b_rel 02
*l0002!rxconfigdata0 gpr_b_rel 08
*$l0002!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0003!temp_reg gpr_b_rel 0D
*l0003!temp gpr_b_rel 0E
*l0004!rxupcontrol gpr_b_rel 0C
*$l0004!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0005!rxconfigdata0 gpr_b_rel 0D
*$l0005!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0006!cellcount gpr_b_rel 0F
*l0006!freelist gpr_b_rel 00
*$l0006!s0 sram_rel 00 0 both 3 0x14
*$l0006!s1 sram_rel 01 0 both 2 0x14
*$l0006!s2 sram_rel 02 0 both 1 0x14
;*l0006!tmp!!2 gpr_b_rel 0E
;*l0006!tmp!!3 gpr_b_rel 0E
;*l0006!tmp!!4 gpr_a_rel 07
*l0006!tmp gpr_b_rel 0E
*$l0007!scratch_base sram_rel 00 0 both 1 0x0
*$l0007!scratch_head sram_rel 01 0 both 1 0x0
*$l0007!scratch_tail sram_rel 02 0 both 1 0x0
*l0008!rbufoffset gpr_b_rel 07
;*l0008!refcnt!!2 gpr_a_rel 06
*l0008!refcnt gpr_b_rel 08
;*l0008!temp!!2 gpr_b_rel 09
;*l0008!temp!!3 gpr_b_rel 09
*l0008!temp gpr_b_rel 09
*$l0009!temp0 sram_rel 00 0 both 1 0x0
*l0007!scratch_sig3 signal 03 0
*l0007!scratch_sig2 signal 02 0
*l0007!scratch_sig1 signal 01 0
*l0006!qa_init signal 01 0
*l0006!qa_init!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig_thd signal 01 0
*l0000!sram_sig signal 01 0
*l0000!dram_sig signal 02 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var $l0009!temp0 0 R
.%liverange 0 $W0 126:131
.%liverange 0 ~$W0 89:90
.%liverange 0 $R0 132:132
.%var l0008!temp 0 R
.%liverange 0 B9 121:131
.%liverange 0 ~B9 89:120
.%var l0008!refcnt 0 R
.%liverange 0 B8 115:118
.%liverange 0 A6 119:131
.%liverange 0 ~A6 89:114
.%var l0008!rbufoffset 0 R
.%liverange 0 B7 120:131
.%liverange 0 ~B7 89:119
.%var $l0007!scratch_tail 0 R
.%liverange 0 $W2 81:88
.%liverange 0 ~$W2 89:131
.%liverange 0 $R2 132:132
.%var $l0007!scratch_head 0 R
.%liverange 0 $W1 80:88
.%liverange 0 ~$W1 89:131
.%liverange 0 $R1 132:132
.%var $l0007!scratch_base 0 R
.%liverange 0 $W0 82:88
.%liverange 0 ~$W0 89:90
.%liverange 0 $R0 132:132
.%var l0006!tmp 0 R
.%liverange 0 B14 62:68
.%liverange 0 A7 69:88
.%liverange 0 ~A7 89:131
.%var $l0006!s2 0 R
.%liverange 0 $W2 66:80
.%liverange 0 $R2 132:132
.%var $l0006!s1 0 R
.%liverange 0 $W1 65:79
.%liverange 0 $R1 132:132
.%var $l0006!s0 0 R
.%liverange 0 $W0 64:81
.%liverange 0 $R0 132:132
.%var l0006!freelist 0 R
.%liverange 0 B0 72:88
.%liverange 0 ~B0 89:93
.%var l0006!cellcount 0 R
.%liverange 0 B15 74:88
.%liverange 0 ~B15 89:131
.%var $l0005!rxconfigdata0 0 R
.%liverange 0 $W0 59:63
.%liverange 0 $R0 132:132
.%var l0005!rxconfigdata0 0 R
.%liverange 0 B13 57:88
.%liverange 0 ~B13 89:131
.%var $l0004!rxconfigdata0 0 R
.%liverange 0 $W0 48:58
.%liverange 0 $R0 132:132
.%var l0004!rxupcontrol 0 R
.%liverange 0 B12 47:88
.%liverange 0 ~B12 89:91
.%var l0003!temp 0 R
.%liverange 0 B14 42:61
.%liverange 0 ~B14 41:41
.%var l0003!temp_reg 0 R
.%liverange 0 B13 41:56
.%var $l0002!rxconfigdata0 0 R
.%liverange 0 $W0 38:47
.%liverange 0 $R0 132:132
.%var l0002!rxconfigdata0 0 R
.%liverange 0 B8 36:88
.%liverange 0 ~B8 89:114
.%var l0001!cur_ctx 0 R
.%liverange 0 B2 17:88
.%liverange 0 ~B2 89:94
.%var l0001!cur_me 0 R
.%liverange 0 B1 16:88
.%liverange 0 ~B1 89:92
.%var l0001!temp 0 R
.%liverange 0 B5 15:21
.%var $l0000!sr0 0 R
.%liverange 0 $W0 91:125
.%liverange 0 $R0 70:88 91:131
.%liverange 0 ~$R0 89:90
.%var l0000!pkt_buff_addr 0 R
.%liverange 0 B6 91:131
.%liverange 0 ~B6 89:90
.%var l0000!rel 0 R
.%liverange 0 B11 109:111
.%liverange 0 ~B11 89:108 112:131
.%var l0000!freebuffer 0 R
.%liverange 0 B10 91:131
.%liverange 0 ~B10 89:90
.%var l0000!t0 0 R
.%liverange 0 B5 22:131
.%var l0000!sram_channel_number 0 R
.%liverange 0 B4 21:29
.%var l0000!sramdescbase 0 R
.%liverange 0 A5 23:131
.%var l0000!drampacketbase 0 R
.%liverange 0 A4 19:131
.%var l0000!elementdone_addr 0 R
.%liverange 0 B4 30:131
.%var l0000!threadfreelist_addr 0 R
.%liverange 0 B3 2:2 5:5 8:8 11:11 13:131
.%var l0000!msfaddress 0 R
.%liverange 0 B7 39:88
.%liverange 0 ~B7 89:119
.%var l0000!ring_num 0 R
.%liverange 0 B6 32:88
.%liverange 0 ~B6 89:90
.%var l0000!rbuf 0 R
.%liverange 0 A3 31:131
.%var l0000!rxconfigdata 0 R
.%liverange 0 B0 28:28
.%liverange 0 A2 29:131
.%var l0000!total_bytes_rx 0 R
.%liverange 0 A1 18:131
.%var l0000!sopeop 0 R
.%liverange 0 A0 96:131
.%liverange 0 ~A0 89:95
.%var l0000!rx_channel_num 0 R
.%liverange 0 B2 95:131
.%liverange 0 ~B2 89:94
.%var l0000!error 0 R
.%liverange 0 B12 92:131
.%liverange 0 ~B12 89:91
.%var l0000!elem 0 R
.%liverange 0 B1 93:131
.%liverange 0 ~B1 89:92
.%var l0000!bytecnt 0 R
.%liverange 0 B0 94:131
.%liverange 0 ~B0 89:93
.%var l0000!rxthreadlist 0 R
.%liverange 0 A8 25:26
.%liverange 0 B15 27:73
.%liverange 0 ~B15 89:131
.%var $l0000!transferreg01 0 R
.%liverange 0 $W2 132:132
.%liverange 0 $R2 132:132
.%var $l0000!transferreg00 0 R
.%liverange 0 $W1 0:64
.%liverange 0 ~$W1 89:131
.%liverange 0 $R1 0:131
.%var l0007!scratch_sig3 1 R
.%liverange 0 G3 85:86
.%var l0007!scratch_sig2 1 R
.%liverange 0 G2 84:86
.%var l0007!scratch_sig1 1 R
.%liverange 0 G1 83:86
.%var l0006!qa_init 1 R
.%liverange 0 G1 67:67 70:70
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:11 13:34
.%var l0000!rx_sig_thd 1 R
.%liverange 0 G1 89:91
.%var l0000!sram_sig 1 R
.%liverange 0 G1 107:107
.%var l0000!dram_sig 1 R
.%liverange 0 D2 124:125
.%var l0000!msf_sig 1 R
.%liverange 0 G1 40:40 50:50 52:52 54:54 56:56 61:61 127:127
.%scope end
.0 D800C00011 common_code