media_lb_pl_on_sf_iface_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.1.55
+uca_date: Mar 24 2003 00:16:30
+current_date: Thu Apr 24 10:00:44 2003

.cpu_version 0x00000002 16 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:init_all# 5
:init_value# 0
:l000_01# 19
:l000_end# 19
:l001_01# 114
:l001_end# 114
:next_packet# 69
:refcnt_calc_done# 93
:start# 69
:wait_for_packet_data# 70
*-- no_destination 0
;*l0000!msfaddress!!2 gpr_b_rel 09
;*l0000!msfaddress!!3 gpr_b_rel 09
;*l0000!msfaddress!!4 gpr_b_rel 09
;*l0000!msfaddress!!5 gpr_b_rel 09
;*l0000!msfaddress!!6 gpr_b_rel 09
;*l0000!msfaddress!!7 gpr_a_rel 00
;*l0000!msfaddress!!8 gpr_b_rel 09
*l0000!msfaddress gpr_b_rel 09
*l0000!get_ring_num gpr_a_rel 01
*l0000!put_ring_num gpr_b_rel 00
*@l0000!packet_count gpr_b_abs 01
;*l0000!port_count!!2 gpr_a_rel 02
*l0000!port_count gpr_a_rel 02
*l0000!byte_count gpr_a_rel 03
*l0000!cur_ctx gpr_a_rel 04
;*l0000!txconfigdata0!!2 gpr_b_rel 0A
;*l0000!txconfigdata0!!3 gpr_b_rel 0A
*l0000!txconfigdata0 gpr_b_rel 0A
*$l0000!txconfigdata0 sram_rel 00 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x24
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x24
*l0000!tbuf_element gpr_b_rel 02
*l0000!tbuf_1st_element gpr_b_rel 03
*l0000!tbuf_mask gpr_b_rel 04
;*l0000!dram_addr!!2 gpr_b_rel 05
*l0000!dram_addr gpr_b_rel 05
*l0000!tbuf gpr_a_rel 05
*l0001!temp gpr_b_rel 0F
*$l0002!scratch_base sram_rel 00 0 both 1 0x0
*$l0002!scratch_head sram_rel 01 0 both 1 0x0
*$l0002!scratch_tail sram_rel 02 0 both 1 0x0
*$l0003!packet_info sram_rel 00 0 both 1 0x0
*l0003!mask gpr_b_rel 0D
;*l0004!tmp_addr!!2 gpr_b_rel 0B
*l0004!tmp_addr gpr_b_rel 0B
*$l0004!tmp_data sram_rel 00 0 both 1 0x0
;*l0005!tbuf_addr!!2 gpr_b_rel 06
;*l0005!tbuf_addr!!3 gpr_a_rel 06
*l0005!tbuf_addr gpr_b_rel 06
;*l0005!refcnt!!2 gpr_b_rel 07
;*l0005!refcnt!!3 gpr_b_rel 07
*l0005!refcnt gpr_b_rel 07
;*l0006!tmp_addr!!2 gpr_b_rel 08
*l0006!tmp_addr gpr_b_rel 08
*$l0006!tmp_data sram_rel 00 0 both 1 0x0
*l0007!temp gpr_b_rel 0C
*$l0008!scratch_data sram_rel 00 0 both 1 0x0
*l0008!temp gpr_b_rel 0E
*l0008!scratch_sig signal 01 0
*l0006!tmp_scratch_sig signal 01 0
*l0004!tmp_scratch_sig signal 01 0
*l0004!tmp_scratch_sig!!2 signal 01 0
*l0003!scratch_sig signal 01 0
*l0002!scratch_sig3 signal 03 0
*l0002!scratch_sig3!!5 signal 03 0
*l0002!scratch_sig3!!4 signal 03 0
*l0002!scratch_sig3!!3 signal 03 0
*l0002!scratch_sig3!!2 signal 03 0
*l0002!scratch_sig2 signal 02 0
*l0002!scratch_sig2!!5 signal 02 0
*l0002!scratch_sig2!!4 signal 02 0
*l0002!scratch_sig2!!3 signal 02 0
*l0002!scratch_sig2!!2 signal 02 0
*l0002!scratch_sig1 signal 01 0
*l0002!scratch_sig1!!5 signal 01 0
*l0002!scratch_sig1!!4 signal 01 0
*l0002!scratch_sig1!!3 signal 01 0
*l0002!scratch_sig1!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!dram_sig signal 02 0
.%type R
.%type SI
.%scope global
.%var l0008!temp 0 R
.%liverange 0 B14 110:114
.%liverange 0 ~B14 69:109
.%var $l0008!scratch_data 0 R
.%liverange 0 $W0 113:113
.%liverange 0 ~$W0 69:78 114:114
.%liverange 0 $R0 115:115
.%var l0007!temp 0 R
.%liverange 0 B12 105:114
.%liverange 0 ~B12 69:104
.%var $l0006!tmp_data 0 R
.%liverange 0 $W0 100:105
.%liverange 0 $R0 115:115
.%var l0006!tmp_addr 0 R
.%liverange 0 B8 98:114
.%liverange 0 ~B8 69:97
.%var l0005!refcnt 0 R
.%liverange 0 B7 90:114
.%liverange 0 ~B7 69:89
.%var l0005!tbuf_addr 0 R
.%liverange 0 B6 86:87
.%liverange 0 A6 88:114
.%liverange 0 ~A6 69:85
.%var $l0004!tmp_data 0 R
.%liverange 0 $W0 79:99
.%liverange 0 $R0 115:115
.%var l0004!tmp_addr 0 R
.%liverange 0 B11 77:114
.%liverange 0 ~B11 69:76
.%var l0003!mask 0 R
.%liverange 0 B13 70:114
.%liverange 0 ~B13 69:69
.%var $l0003!packet_info 0 R
.%liverange 0 $W0 115:115
.%liverange 0 $R0 71:114
.%liverange 0 ~$R0 69:70
.%var $l0002!scratch_tail 0 R
.%liverange 0 $W2 41:68
.%liverange 0 ~$W2 69:114
.%liverange 0 $R2 115:115
.%var $l0002!scratch_head 0 R
.%liverange 0 $W1 40:68
.%liverange 0 ~$W1 69:106
.%liverange 0 $R1 115:115
.%var $l0002!scratch_base 0 R
.%liverange 0 $W0 42:68
.%liverange 0 ~$W0 69:78
.%liverange 0 $R0 115:115
.%var l0001!temp 0 R
.%liverange 0 B15 7:114
.%var l0000!tbuf 0 R
.%liverange 0 A5 9:114
.%var l0000!dram_addr 0 R
.%liverange 0 B5 74:114
.%liverange 0 ~B5 69:73
.%var l0000!tbuf_mask 0 R
.%liverange 0 B4 10:114
.%var l0000!tbuf_1st_element 0 R
.%liverange 0 B3 13:114
.%var l0000!tbuf_element 0 R
.%liverange 0 B2 83:114
.%liverange 0 ~B2 69:82
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 107:114
.%liverange 0 ~$W1 69:106
.%liverange 0 $R1 115:115
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 106:112
.%liverange 0 ~$W0 69:78 114:114
.%liverange 0 $R0 115:115
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W0 23:41
.%liverange 0 $R0 115:115
.%var l0000!txconfigdata0 0 R
.%liverange 0 B10 21:68
.%liverange 0 ~B10 69:114
.%var l0000!cur_ctx 0 R
.%liverange 0 A4 8:114
.%var l0000!byte_count 0 R
.%liverange 0 A3 72:114
.%liverange 0 ~A3 69:71
.%var l0000!port_count 0 R
.%liverange 0 A2 12:114
.%var @l0000!packet_count 0 R
.%liverange 0 @B1 0:114
.%var l0000!put_ring_num 0 R
.%liverange 0 B0 15:114
.%var l0000!get_ring_num 0 R
.%liverange 0 A1 14:114
.%var l0000!msfaddress 0 R
.%liverange 0 B9 20:68 104:114
.%liverange 0 ~B9 69:102
.%liverange 0 A0 103:103
.%var l0008!scratch_sig 1 R
.%liverange 0 G1 114:114
.%var l0006!tmp_scratch_sig 1 R
.%liverange 0 G1 101:101
.%var l0004!tmp_scratch_sig 1 R
.%liverange 0 G1 80:80 82:82
.%var l0003!scratch_sig 1 R
.%liverange 0 G1 71:71
.%var l0002!scratch_sig3 1 R
.%liverange 0 G3 45:46 50:51 55:56 60:61 65:66
.%var l0002!scratch_sig2 1 R
.%liverange 0 G2 44:46 49:51 54:56 59:61 64:66
.%var l0002!scratch_sig1 1 R
.%liverange 0 G1 43:46 48:51 53:56 58:61 63:66
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:3 5:18
.%var l0000!msf_sig 1 R
.%liverange 0 G1 24:24 28:28 30:30 32:32 34:34 39:39 108:108
.%var l0000!dram_sig 1 R
.%liverange 0 D2 97:102
.%scope end
.0 D801400010 common_code
	.import_var __chip_id __chip_revision __uengine_id
	.%line 55 "C:\Angel-Island\diag\test_suites\microcode\media_lb_pl_on_sf_iface\media_lb_pl_on_sf_iface_tx.uc" 1 0
	.reg l0000!msfaddress l0000!msfaddress0 l0000!msfaddress1
	.%line 56 "C:\Angel-Island\diag\test_suites\microcode\media_lb_pl_on_sf_iface\media_lb_pl_on_sf_iface_tx.uc" 1 0
	.reg l0000!pci_base l0000!get_ring_num l0000!put_ring_num @l0000!packet_count
	.%line 57 "C:\Angel-Island\diag\test_suites\microcode\media_lb_pl_on_sf_iface\media_lb_pl_on_sf_iface_tx.uc" 1 0
	.reg l0000!port_count
	.%line 58 "C:\Angel-Island\diag\test_suites\microcode\media_lb_pl_on_sf_iface\media_lb_pl_on_sf_iface_tx.uc" 1 0
	.reg l0000!byte_count l0000!cur_ctx