media_lb_pl_on_sf_iface_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.1.55
+uca_date: Mar 24 2003 00:16:30
+current_date: Thu Apr 24 10:00:44 2003

.cpu_version 0x00000002 16 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:cont_init1# 13
:cont_init2# 33
:init_rbuf# 40
:init_value# 0
:not_ctx_0# 3
:not_ctx_1# 6
:not_ctx_2# 9
:not_ctx_3# 12
:receivepacket# 90
:rsw# 92
:set_refcnt_overwrite_bit# 100
*-- no_destination 0
*$l0000!transferreg00 sram_rel 00 0 both 2 0x38
*$l0000!transferreg01 sram_rel 01 0 both 1 0x38
;*l0000!rxthreadlist!!2 gpr_b_rel 05
;*l0000!rxthreadlist!!3 gpr_b_rel 05
*l0000!rxthreadlist gpr_a_rel 07
*l0000!bytecnt gpr_a_rel 00
*l0000!elem gpr_a_rel 01
*l0000!error gpr_b_rel 0A
*l0000!rx_channel_num gpr_b_rel 00
*l0000!cur_ctx gpr_a_rel 06
*@l0000!packet_count gpr_b_abs 01
;*l0000!rxconfigdata!!2 gpr_a_rel 02
*l0000!rxconfigdata gpr_b_rel 06
*l0000!rbuf gpr_a_rel 03
*l0000!ring_num gpr_b_rel 00
;*l0000!msfaddress!!2 gpr_b_rel 0B
;*l0000!msfaddress!!3 gpr_b_rel 0B
;*l0000!msfaddress!!4 gpr_b_rel 0B
;*l0000!msfaddress!!5 gpr_b_rel 0B
;*l0000!msfaddress!!6 gpr_b_rel 0B
*l0000!msfaddress gpr_b_rel 0B
*l0000!threadfreelist_addr gpr_b_rel 02
*l0000!elementdone_addr gpr_a_rel 04
;*l0000!drampacketbase!!2 gpr_b_rel 03
*l0000!drampacketbase gpr_b_rel 03
*l0000!put_ring_num gpr_b_rel 04
*l0000!rx_count_ring_num gpr_b_rel 04
*l0001!temp gpr_b_rel 03
*l0001!cur_me gpr_b_rel 0F
*l0002!rxconfigdata0 gpr_b_rel 0C
*$l0002!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0003!temp_reg gpr_b_rel 05
*l0003!temp gpr_b_rel 06
*l0004!rxupcontrol gpr_b_rel 0D
*$l0004!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0005!rxconfigdata0 gpr_b_rel 0E
*$l0005!rxconfigdata0 sram_rel 00 0 both 1 0x0
*$l0006!scratch_base sram_rel 00 0 both 1 0x0
*$l0006!scratch_head sram_rel 01 0 both 1 0x0
*$l0006!scratch_tail sram_rel 02 0 both 1 0x0
*l0007!rbufoffset gpr_b_rel 07
;*l0007!refcnt!!2 gpr_a_rel 05
*l0007!refcnt gpr_b_rel 08
;*l0007!temp!!2 gpr_b_rel 09
;*l0007!temp!!3 gpr_b_rel 09
*l0007!temp gpr_b_rel 09
*$l0008!temp0 sram_rel 00 0 both 1 0x0
*$l0009!scratch_packet_count sram_rel 00 0 both 1 0x0
*l0009!scratch_sig signal 01 0
*l0006!scratch_sig3 signal 03 0
*l0006!scratch_sig3!!5 signal 03 0
*l0006!scratch_sig3!!4 signal 03 0
*l0006!scratch_sig3!!3 signal 03 0
*l0006!scratch_sig3!!2 signal 03 0
*l0006!scratch_sig2 signal 02 0
*l0006!scratch_sig2!!5 signal 02 0
*l0006!scratch_sig2!!4 signal 02 0
*l0006!scratch_sig2!!3 signal 02 0
*l0006!scratch_sig2!!2 signal 02 0
*l0006!scratch_sig1 signal 01 0
*l0006!scratch_sig1!!5 signal 01 0
*l0006!scratch_sig1!!4 signal 01 0
*l0006!scratch_sig1!!3 signal 01 0
*l0006!scratch_sig1!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig_thd signal 01 0
*l0000!sig_dram_xfer1 signal 02 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var $l0009!scratch_packet_count 0 R
.%liverange 0 $W0 111:112
.%liverange 0 ~$W0 90:107
.%liverange 0 $R0 113:113
.%var $l0008!temp0 0 R
.%liverange 0 $W0 108:110
.%liverange 0 $R0 113:113
.%var l0007!temp 0 R
.%liverange 0 B9 103:112
.%liverange 0 ~B9 90:102
.%var l0007!refcnt 0 R
.%liverange 0 B8 97:100
.%liverange 0 A5 101:112
.%liverange 0 ~A5 90:96
.%var l0007!rbufoffset 0 R
.%liverange 0 B7 102:112
.%liverange 0 ~B7 90:101
.%var $l0006!scratch_tail 0 R
.%liverange 0 $W2 62:89
.%liverange 0 ~$W2 90:112
.%liverange 0 $R2 113:113
.%var $l0006!scratch_head 0 R
.%liverange 0 $W1 61:89
.%liverange 0 ~$W1 90:112
.%liverange 0 $R1 113:113
.%var $l0006!scratch_base 0 R
.%liverange 0 $W0 63:89
.%liverange 0 ~$W0 90:107
.%liverange 0 $R0 113:113
.%var $l0005!rxconfigdata0 0 R
.%liverange 0 $W0 58:62
.%liverange 0 $R0 113:113
.%var l0005!rxconfigdata0 0 R
.%liverange 0 B14 56:89
.%liverange 0 ~B14 90:112
.%var $l0004!rxconfigdata0 0 R
.%liverange 0 $W0 47:57
.%liverange 0 $R0 113:113
.%var l0004!rxupcontrol 0 R
.%liverange 0 B13 46:89
.%liverange 0 ~B13 90:112
.%var l0003!temp 0 R
.%liverange 0 B6 41:89
.%liverange 0 ~B6 40:40 90:112
.%var l0003!temp_reg 0 R
.%liverange 0 B5 40:89
.%liverange 0 ~B5 90:112
.%var $l0002!rxconfigdata0 0 R
.%liverange 0 $W0 37:46
.%liverange 0 $R0 113:113
.%var l0002!rxconfigdata0 0 R
.%liverange 0 B12 35:89
.%liverange 0 ~B12 90:112
.%var l0001!cur_me 0 R
.%liverange 0 B15 16:112
.%var l0001!temp 0 R
.%liverange 0 B3 15:23
.%var l0000!rx_count_ring_num 0 R
.%liverange 0 B4 28:112
.%var l0000!put_ring_num 0 R
.%liverange 0 B4 27:27
.%var l0000!drampacketbase 0 R
.%liverange 0 B3 24:112
.%var l0000!elementdone_addr 0 R
.%liverange 0 A4 29:112
.%var l0000!threadfreelist_addr 0 R
.%liverange 0 B2 2:2 5:5 8:8 11:11 13:112
.%var l0000!msfaddress 0 R
.%liverange 0 B11 38:89
.%liverange 0 ~B11 90:112
.%var l0000!ring_num 0 R
.%liverange 0 B0 18:89
.%liverange 0 ~B0 90:95
.%var l0000!rbuf 0 R
.%liverange 0 A3 30:112
.%var l0000!rxconfigdata 0 R
.%liverange 0 B6 22:22
.%liverange 0 A2 23:112
.%var @l0000!packet_count 0 R
.%liverange 0 @B1 0:112
.%var l0000!cur_ctx 0 R
.%liverange 0 A6 17:112
.%var l0000!rx_channel_num 0 R
.%liverange 0 B0 96:112
.%liverange 0 ~B0 90:95
.%var l0000!error 0 R
.%liverange 0 B10 95:112
.%liverange 0 ~B10 90:94
.%var l0000!elem 0 R
.%liverange 0 A1 93:112
.%liverange 0 ~A1 90:92
.%var l0000!bytecnt 0 R
.%liverange 0 A0 94:112
.%liverange 0 ~A0 90:93
.%var l0000!rxthreadlist 0 R
.%liverange 0 A7 19:19
.%liverange 0 B5 20:39
.%liverange 0 ~B5 90:112
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 113:113
.%liverange 0 $R1 113:113
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:36
.%liverange 0 ~$W0 90:107
.%liverange 0 $R0 0:112
.%var l0009!scratch_sig 1 R
.%liverange 0 G1 112:112
.%var l0006!scratch_sig3 1 R
.%liverange 0 G3 66:67 71:72 76:77 81:82 86:87
.%var l0006!scratch_sig2 1 R
.%liverange 0 G2 65:67 70:72 75:77 80:82 85:87
.%var l0006!scratch_sig1 1 R
.%liverange 0 G1 64:67 69:72 74:77 79:82 84:87
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:11 13:32
.%var l0000!rx_sig_thd 1 R
.%liverange 0 G1 90:92
.%var l0000!sig_dram_xfer1 1 R
.%liverange 0 D2 106:107
.%var l0000!msf_sig 1 R
.%liverange 0 G1 39:39 49:49 51:51 53:53 55:55 60:60 109:109
.%scope end
.0 D800C00011 common_code
	.import_var __chip_id __chip_revision __uengine_id
	.%line 52 "C:\Angel-Island\diag\test_suites\microcode\media_lb_pl_on_sf_iface\media_lb_pl_on_sf_iface_rx.uc" 1 0
	.reg $l0000!transferreg00 $l0000!transferreg01
	.%line 53 "C:\Angel-Island\diag\test_suites\microcode\media_lb_pl_on_sf_iface\media_lb_pl_on_sf_iface_rx.uc" 1 0
	.reg l0000!rxthreadlist l0000!bytecnt l0000!elem l0000!error l0000!rx_channel_num