media_loopback_bw_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.0.411
+uca_date: Sep  9 2002 00:25:20
+current_date: Tue Oct 29 18:34:34 2002

.cpu_version 0x00000002 0 15

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:cont1# 88
:init_all# 5
:init_value# 0
:l000_01# 19
:l000_end# 19
:l001_01# 106
:l001_02# 110
:l001_03# 114
:l001_end# 115
:next_packet# 66
:start# 66
:wait_for_dram_addr# 70
:wait_for_packet_data# 67
*-- no_destination 0
;*l0000!msfaddress!!2 gpr_b_rel 08
;*l0000!msfaddress!!3 gpr_b_rel 08
;*l0000!msfaddress!!4 gpr_b_rel 08
;*l0000!msfaddress!!5 gpr_b_rel 08
;*l0000!msfaddress!!6 gpr_b_rel 08
;*l0000!msfaddress!!7 gpr_a_rel 00
;*l0000!msfaddress!!8 gpr_b_rel 08
*l0000!msfaddress gpr_b_rel 08
*l0000!get_ring_num gpr_a_rel 01
*l0000!put_ring_num gpr_b_rel 00
*@l0000!packet_count gpr_b_abs 01
;*l0000!port_count!!2 gpr_a_rel 02
*l0000!port_count gpr_a_rel 02
*l0000!byte_count gpr_a_rel 03
*l0000!cur_ctx gpr_a_rel 04
;*l0000!txconfigdata0!!2 gpr_b_rel 09
;*l0000!txconfigdata0!!3 gpr_b_rel 09
*l0000!txconfigdata0 gpr_b_rel 09
*$l0000!txconfigdata0 sram_rel 00 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x1D
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x1D
*l0000!tbuf_element gpr_b_rel 02
*l0000!tbuf_1st_element gpr_b_rel 03
*l0000!tbuf_mask gpr_b_rel 04
;*l0000!dram_addr!!2 gpr_b_rel 05
*l0000!dram_addr gpr_b_rel 05
*l0000!tbuf gpr_a_rel 05
*l0001!temp gpr_b_rel 0C
*$l0002!scratch_base sram_rel 00 0 both 1 0x0
*$l0002!scratch_head sram_rel 01 0 both 1 0x0
*$l0002!scratch_tail sram_rel 02 0 both 1 0x0
*$l0003!packet_info sram_rel 00 0 both 1 0x0
*l0003!mask gpr_b_rel 0B
*$l0004!dram_base sram_rel 00 0 both 1 0x0
;*l0005!tbuf_addr!!2 gpr_b_rel 06
;*l0005!tbuf_addr!!3 gpr_a_rel 06
*l0005!tbuf_addr gpr_b_rel 06
;*l0005!refcnt!!2 gpr_b_rel 07
;*l0005!refcnt!!3 gpr_b_rel 07
*l0005!refcnt gpr_b_rel 07
*l0006!temp gpr_b_rel 0A
*$l0007!scratch_data sram_rel 00 0 both 1 0x0
*l0007!scratch_sig signal 01 0
*l0004!scratch_sig signal 01 0
*l0003!scratch_sig signal 01 0
*l0002!scratch_sig3 signal 03 0
*l0002!scratch_sig3!!5 signal 03 0
*l0002!scratch_sig3!!4 signal 03 0
*l0002!scratch_sig3!!3 signal 03 0
*l0002!scratch_sig3!!2 signal 03 0
*l0002!scratch_sig2 signal 02 0
*l0002!scratch_sig2!!5 signal 02 0
*l0002!scratch_sig2!!4 signal 02 0
*l0002!scratch_sig2!!3 signal 02 0
*l0002!scratch_sig2!!2 signal 02 0
*l0002!scratch_sig1 signal 01 0
*l0002!scratch_sig1!!5 signal 01 0
*l0002!scratch_sig1!!4 signal 01 0
*l0002!scratch_sig1!!3 signal 01 0
*l0002!scratch_sig1!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!dram_sig signal 02 0
.%type R
.%type SI
.%scope global
.%var $l0007!scratch_data 0 R
.%liverange 0 $W0 101:116
.%liverange 0 ~$W0 66:96
.%liverange 0 $R0 117:117
.%var l0006!temp 0 R
.%liverange 0 B10 96:116
.%liverange 0 ~B10 66:95
.%var l0005!refcnt 0 R
.%liverange 0 B7 83:116
.%liverange 0 ~B7 66:82
.%var l0005!tbuf_addr 0 R
.%liverange 0 B6 79:80
.%liverange 0 A6 81:116
.%liverange 0 ~A6 66:78
.%var $l0004!dram_base 0 R
.%liverange 0 $W0 117:117
.%liverange 0 $R0 71:116
.%liverange 0 ~$R0 66:67 70:70
.%var l0003!mask 0 R
.%liverange 0 B11 67:116
.%liverange 0 ~B11 66:66
.%var $l0003!packet_info 0 R
.%liverange 0 $W0 117:117
.%liverange 0 $R0 68:69
.%liverange 0 ~$R0 67:67 70:70
.%var $l0002!scratch_tail 0 R
.%liverange 0 $W2 41:65
.%liverange 0 ~$W2 66:116
.%liverange 0 $R2 117:117
.%var $l0002!scratch_head 0 R
.%liverange 0 $W1 40:65
.%liverange 0 ~$W1 66:97
.%liverange 0 $R1 117:117
.%var $l0002!scratch_base 0 R
.%liverange 0 $W0 42:65
.%liverange 0 ~$W0 66:96
.%liverange 0 $R0 117:117
.%var l0001!temp 0 R
.%liverange 0 B12 7:116
.%var l0000!tbuf 0 R
.%liverange 0 A5 9:116
.%var l0000!dram_addr 0 R
.%liverange 0 B5 74:116
.%liverange 0 ~B5 66:73
.%var l0000!tbuf_mask 0 R
.%liverange 0 B4 10:116
.%var l0000!tbuf_1st_element 0 R
.%liverange 0 B3 13:116
.%var l0000!tbuf_element 0 R
.%liverange 0 B2 76:116
.%liverange 0 ~B2 66:75
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 98:116
.%liverange 0 ~$W1 66:97
.%liverange 0 $R1 117:117
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 97:100
.%liverange 0 $R0 117:117
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W0 23:41
.%liverange 0 $R0 117:117
.%var l0000!txconfigdata0 0 R
.%liverange 0 B9 21:65
.%liverange 0 ~B9 66:116
.%var l0000!cur_ctx 0 R
.%liverange 0 A4 8:116
.%var l0000!byte_count 0 R
.%liverange 0 A3 69:116
.%liverange 0 ~A3 66:68
.%var l0000!port_count 0 R
.%liverange 0 A2 12:116
.%var @l0000!packet_count 0 R
.%liverange 0 @B1 0:116
.%var l0000!put_ring_num 0 R
.%liverange 0 B0 15:116
.%var l0000!get_ring_num 0 R
.%liverange 0 A1 14:116
.%var l0000!msfaddress 0 R
.%liverange 0 B8 20:65 95:116
.%liverange 0 ~B8 66:93
.%liverange 0 A0 94:94
.%var l0007!scratch_sig 1 R
.%liverange 0 G1 102:102
.%var l0004!scratch_sig 1 R
.%liverange 0 G1 71:71
.%var l0003!scratch_sig 1 R
.%liverange 0 G1 68:68
.%var l0002!scratch_sig3 1 R
.%liverange 0 G3 45:46 50:51 55:56 60:61 65:66
.%var l0002!scratch_sig2 1 R
.%liverange 0 G2 44:46 49:51 54:56 59:61 64:66
.%var l0002!scratch_sig1 1 R
.%liverange 0 G1 43:46 48:51 53:56 58:61 63:66
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 0:3 5:18 115:116
.%var l0000!msf_sig 1 R
.%liverange 0 G1 24:24 28:28 30:30 32:32 34:34 39:39 99:99
.%var l0000!dram_sig 1 R
.%liverange 0 D2 92:93
.%scope end
.0 D801400010 common_code
	.import_var __chip_id __chip_revision __uengine_id
	.%line 61 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.reg l0000!msfaddress l0000!msfaddress0 l0000!msfaddress1
	.%line 62 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.reg l0000!pci_base l0000!get_ring_num l0000!put_ring_num @l0000!packet_count
	.%line 63 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.reg l0000!port_count
	.%line 64 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.reg l0000!byte_count l0000!cur_ctx
	.%line 65 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.reg l0000!txconfigdata0
	.%line 66 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.reg $l0000!txconfigdata0
	.%line 67 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 68 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.reg l0000!tbuf_element l0000!tbuf_1st_element l0000!tbuf_mask
	.%line 69 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.reg l0000!dram_addr l0000!tbuf
	.%line 70 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.sig l0000!dram_sig l0000!msf_sig l0000!interthd_sig
	.%line 72 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.xfer_order $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 74 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0
	.addr l0000!interthd_sig 15
	.%line 75 "C:\Angel-Island\diag\test_suites\microcode\media_loopback_bw\media_loopback_bw_tx.uc" 1 0