line_rate_bw_eg_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Mon Mar 22 11:08:06 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:addfreelist# 71
:check_ring0_full# 166
:check_ring1_full# 170
:check_ring2_full# 174
:check_ring3_full# 178
:init_rbuf# 33
:init_thread0_only# 20
:next_packet# 184
:null# 184
:port0# 165
:port1# 169
:port2# 173
:port3# 177
:put_data_to_scratch# 179
:rbuf_to_dram_done# 163
:receivenextpacket# 128
:rsw# 131
:set_refcnt_overwrite_bit# 145
:wait_for_dram_sig# 159
*-- no_destination 0
*l0000!cur_me gpr_b_rel 0B
*l0000!cur_ctx gpr_a_rel 00
*l0000!sram_channel_number gpr_a_rel 01
*l0000!t0 gpr_a_rel 02
*$l0000!sr0 sram_rel 03 0 both 1 0x0
*l0000!ring gpr_b_rel 0C
;*l0000!rxconfigdata!!2 gpr_a_rel 03
*l0000!rxconfigdata gpr_b_rel 09
*l0000!rbuf_base gpr_a_rel 04
*l0000!rbuf_elem_done gpr_b_rel 02
*l0000!rx_thd_freelist gpr_b_rel 02
*l0000!null gpr_b_rel 0B
*l0000!elem gpr_b_rel 03
;*l0000!bytecnt!!2 gpr_b_rel 04
*l0000!bytecnt gpr_b_rel 04
*$l0000!prepend_data0 sram_rel 00 0 both 2 0x5E
*$l0000!prepend_data1 sram_rel 01 0 both 1 0x5E
*$l0000!ring_data sram_rel 00 0 both 1 0x0
*@l0000!sramdescbase gpr_a_abs 05
*@l0000!drampacketbase gpr_a_abs 15
*$l0000!transferreg00 sram_rel 02 0 both 2 0x56
*$l0000!transferreg01 sram_rel 03 0 both 1 0x56
*l0001!temp_data gpr_b_rel 0C
;*l0002!rxthreadlist!!2 gpr_b_rel 0D
;*l0002!rxthreadlist!!3 gpr_b_rel 0D
*l0002!rxthreadlist gpr_a_rel 06
*l0002!temp_data gpr_a_rel 07
;*l0002!me_data!!2 gpr_b_rel 0D
*l0002!me_data gpr_b_rel 0D
*l0003!msfaddress gpr_b_rel 0E
*l0003!rxcontroldata gpr_b_rel 0F
*$l0003!rxcontroldata sram_rel 00 0 both 1 0x0
*l0004!msfaddress gpr_b_rel 00
*$l0004!csixtypemapdata sram_rel 00 0 both 1 0x0
*l0005!temp_reg gpr_b_rel 0E
*l0005!rbufelemdonedata gpr_b_rel 0F
;*l0006!timeout_val!!2 gpr_b_rel 01
*l0006!timeout_val gpr_b_rel 01
*l0007!msfaddress gpr_b_rel 00
*l0007!txcontroldata gpr_b_rel 01
*$l0007!txcontroldata sram_rel 00 0 both 1 0x0
;*l0008!msfaddress!!2 gpr_b_rel 03
;*l0008!msfaddress!!3 gpr_b_rel 03
;*l0008!msfaddress!!4 gpr_b_rel 03
*l0008!msfaddress gpr_b_rel 03
*l0008!txupcontroldata gpr_b_rel 04
*$l0008!txupcontroldata sram_rel 00 0 both 1 0x0
*l0009!cellcount gpr_b_rel 08
*l0009!freelist gpr_b_rel 09
*$l0009!s0 sram_rel 00 0 both 3 0x31
*$l0009!s1 sram_rel 01 0 both 2 0x31
*$l0009!s2 sram_rel 02 0 both 1 0x31
;*l0009!tmp!!2 gpr_b_rel 0A
;*l0009!tmp!!3 gpr_b_rel 0A
;*l0009!tmp!!4 gpr_b_rel 0A
*l0009!tmp gpr_a_rel 08
*$l0009!sr0 sram_rel 00 0 both 4 0x25
*$l0009!sr1 sram_rel 01 0 both 3 0x25
*$l0009!sr2 sram_rel 02 0 both 2 0x25
*$l0009!sr3 sram_rel 03 0 both 1 0x25
*l0009!sram_desc_base gpr_b_rel 03
*$l0010!scratch_base sram_rel 00 0 both 1 0x0
*$l0010!scratch_head sram_rel 01 0 both 1 0x0
*$l0010!scratch_tail sram_rel 02 0 both 1 0x0
;*l0010!temp_val!!2 gpr_b_rel 06
;*l0010!temp_val!!3 gpr_b_rel 06
;*l0010!temp_val!!4 gpr_b_rel 06
*l0010!temp_val gpr_b_rel 06
*l0011!msfaddress gpr_b_rel 07
*$l0011!rxcontroldata sram_rel 00 0 both 1 0x0
*l0012!msfaddress gpr_b_rel 08
*$l0012!txcontroldata sram_rel 00 0 both 1 0x0
;*l0013!temp!!2 gpr_b_rel 09
;*l0013!temp!!3 gpr_b_rel 09
;*l0013!temp!!4 gpr_b_rel 09
*l0013!temp gpr_b_rel 09
;*l0014!refcnt!!2 gpr_a_rel 09
*l0014!refcnt gpr_b_rel 07
;*l0014!ind_ref_data!!2 gpr_b_rel 05
;*l0014!ind_ref_data!!3 gpr_b_rel 05
*l0014!ind_ref_data gpr_b_rel 05
*l0015!rbufaddress gpr_b_rel 07
*l0016!pkt_buff_addr gpr_b_rel 00
;*l0016!rel!!2 gpr_b_rel 06
*l0016!rel gpr_b_rel 06
*l0016!freebuffer gpr_b_rel 01
*$l0016!sram_data sram_rel 01 0 both 1 0x0
*l0017!jump_offset gpr_b_rel 08
*l0018!rbuf_elem_done_data gpr_b_rel 0B
*l0010!scratch_sig3 signal 03 0
*l0010!scratch_sig3!!4 signal 03 0
*l0010!scratch_sig3!!3 signal 03 0
*l0010!scratch_sig3!!2 signal 03 0
*l0010!scratch_sig2 signal 02 0
*l0010!scratch_sig2!!4 signal 02 0
*l0010!scratch_sig2!!3 signal 02 0
*l0010!scratch_sig2!!2 signal 02 0
*l0010!scratch_sig1 signal 01 0
*l0010!scratch_sig1!!4 signal 01 0
*l0010!scratch_sig1!!3 signal 01 0
*l0010!scratch_sig1!!2 signal 01 0
*l0009!qa_init signal 01 0
*l0009!qa_init!!2 signal 01 0
*l0000!dram_sig signal 04 0
*l0000!sram_sig signal 02 0
*l0000!sram_sig!!2 signal 01 0
*l0000!scratch_sig signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!12 signal 01 0
*l0000!msf_sig!!11 signal 01 0
*l0000!msf_sig!!10 signal 01 0
*l0000!msf_sig!!9 signal 01 0
*l0000!msf_sig!!8 signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!next_ctx_sig signal 0E 0
*l0000!rx_sig signal 01 0
.%type R
.%type SI
.%scope global
.%var l0018!rbuf_elem_done_data 0 R
.%liverange 0 B11 182:183
.%liverange 0 ~B11 128:131 184:184
.%var l0017!jump_offset 0 R
.%liverange 0 B8 164:167 169:171 173:175 177:183
.%liverange 0 ~B8 128:163 184:184
.%var $l0016!sram_data 0 R
.%liverange 0 $W1 156:167 169:171 173:175 177:183
.%liverange 0 ~$W1 128:155 184:184
.%liverange 0 $R1 185:185
.%var l0016!freebuffer 0 R
.%liverange 0 B1 149:167 169:171 173:175 177:183
.%liverange 0 ~B1 128:148 184:184
.%var l0016!rel 0 R
.%liverange 0 B6 150:167 169:171 173:175 177:183
.%liverange 0 ~B6 128:149 184:184
.%var l0016!pkt_buff_addr 0 R
.%liverange 0 B0 152:167 169:171 173:175 177:183
.%liverange 0 ~B0 128:151 184:184
.%var l0015!rbufaddress 0 R
.%liverange 0 B7 136:141
.%var l0014!ind_ref_data 0 R
.%liverange 0 B5 138:167 169:171 173:175 177:183
.%liverange 0 ~B5 128:137 184:184
.%var l0014!refcnt 0 R
.%liverange 0 B7 142:145
.%liverange 0 A9 146:167 169:171 173:175 177:183
.%liverange 0 ~A9 128:141 184:184
.%var l0013!temp 0 R
.%liverange 0 B9 117:127
.%liverange 0 ~B9 128:167 169:171 173:175 177:184
.%var $l0012!txcontroldata 0 R
.%liverange 0 $W0 115:127
.%liverange 0 ~$W0 128:158 184:184
.%liverange 0 $R0 114:127
.%liverange 0 ~$R0 128:136 184:184
.%var l0012!msfaddress 0 R
.%liverange 0 B8 113:127
.%liverange 0 ~B8 128:163 184:184
.%var $l0011!rxcontroldata 0 R
.%liverange 0 $W0 111:114
.%liverange 0 $R0 110:113
.%var l0011!msfaddress 0 R
.%liverange 0 B7 109:127
.%liverange 0 ~B7 128:135 184:184
.%var l0010!temp_val 0 R
.%liverange 0 B6 77:127
.%liverange 0 ~B6 128:149 184:184
.%var $l0010!scratch_tail 0 R
.%liverange 0 $W2 80:127
.%liverange 0 ~$W2 128:167 169:171 173:175 177:184
.%liverange 0 $R2 185:185
.%var $l0010!scratch_head 0 R
.%liverange 0 $W1 79:127
.%liverange 0 ~$W1 128:155 184:184
.%liverange 0 $R1 185:185
.%var $l0010!scratch_base 0 R
.%liverange 0 $W0 78:110
.%liverange 0 $R0 185:185
.%var l0009!sram_desc_base 0 R
.%liverange 0 B3 57:127
.%liverange 0 ~B3 128:134 184:184
.%var $l0009!sr3 0 R
.%liverange 0 $W3 185:185
.%liverange 0 $R3 185:185
.%var $l0009!sr2 0 R
.%liverange 0 $W2 185:185
.%liverange 0 $R2 185:185
.%var $l0009!sr1 0 R
.%liverange 0 $W1 185:185
.%liverange 0 $R1 185:185
.%var $l0009!sr0 0 R
.%liverange 0 $W0 185:185
.%liverange 0 $R0 67:109
.%var l0009!tmp 0 R
.%liverange 0 A8 59:59
.%liverange 0 B10 60:127
.%liverange 0 ~B10 128:167 169:171 173:175 177:184
.%var $l0009!s2 0 R
.%liverange 0 $W2 63:79
.%liverange 0 $R2 185:185
.%var $l0009!s1 0 R
.%liverange 0 $W1 62:78
.%liverange 0 $R1 185:185
.%var $l0009!s0 0 R
.%liverange 0 $W0 61:77
.%liverange 0 $R0 185:185
.%var l0009!freelist 0 R
.%liverange 0 B9 69:116
.%var l0009!cellcount 0 R
.%liverange 0 B8 71:112
.%var $l0008!txupcontroldata 0 R
.%liverange 0 $W0 48:60
.%liverange 0 $R0 185:185
.%var l0008!txupcontroldata 0 R
.%liverange 0 B4 47:127
.%liverange 0 ~B4 128:139 184:184
.%var l0008!msfaddress 0 R
.%liverange 0 B3 49:56
.%var $l0007!txcontroldata 0 R
.%liverange 0 $W0 45:47
.%liverange 0 $R0 185:185
.%var l0007!txcontroldata 0 R
.%liverange 0 B1 43:127
.%liverange 0 ~B1 128:148 184:184
.%var l0007!msfaddress 0 R
.%liverange 0 B0 42:127
.%liverange 0 ~B0 128:151 184:184
.%var l0006!timeout_val 0 R
.%liverange 0 B1 39:42
.%var l0005!rbufelemdonedata 0 R
.%liverange 0 B15 34:127
.%liverange 0 ~B15 33:33 128:167 169:171 173:175 177:184
.%var l0005!temp_reg 0 R
.%liverange 0 B14 33:127
.%liverange 0 ~B14 128:167 169:171 173:175 177:184
.%var $l0004!csixtypemapdata 0 R
.%liverange 0 $W0 30:44
.%liverange 0 $R0 185:185
.%var l0004!msfaddress 0 R
.%liverange 0 B0 31:41
.%var $l0003!rxcontroldata 0 R
.%liverange 0 $W0 27:29
.%liverange 0 $R0 185:185
.%var l0003!rxcontroldata 0 R
.%liverange 0 B15 25:32
.%liverange 0 ~B15 33:33
.%var l0003!msfaddress 0 R
.%liverange 0 B14 28:32
.%var l0002!me_data 0 R