line_rate_bw_in_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Mon Mar 22 11:08:06 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:check_ring_full# 71
:init_done# 34
:init_thread0_only# 29
:l000_01# 8
:l000_02# 12
:l000_03# 16
:l000_end# 17
:next_packet# 76
:null# 76
:rbuf_to_dram_done# 70
:receivenextpacket# 36
:rsw# 39
:set_refcnt_overwrite_bit# 50
:startreceive# 36
:wait_for_dram_sig# 66
:wait_for_inter_me_sig# 33
*-- no_destination 0
*l0000!cur_me gpr_a_rel 07
*l0000!cur_ctx gpr_b_rel 0A
*l0000!sram_channel_number gpr_a_rel 00
*l0000!t0 gpr_b_rel 03
*l0000!ring gpr_b_rel 04
;*l0000!rxconfigdata!!2 gpr_a_rel 01
*l0000!rxconfigdata gpr_b_rel 0D
*$l0000!transferreg00 sram_rel 01 0 both 2 0x20
*$l0000!transferreg01 sram_rel 02 0 both 1 0x20
*l0000!rbuf_base gpr_a_rel 02
*l0000!rbuf_elem_done gpr_b_rel 0B
*l0000!rx_thd_freelist gpr_b_rel 05
*l0000!null gpr_b_rel 0E
*l0000!elem gpr_a_rel 03
*l0000!bytecnt gpr_a_rel 04
*l0000!rx_port_num gpr_b_rel 06
*$l0000!sr0 sram_rel 00 0 both 1 0x0
*$l0000!ring_data sram_rel 00 0 both 1 0x0
*@l0000!sramdescbase gpr_a_abs 05
*@l0000!drampacketbase gpr_a_abs 15
*l0001!temp gpr_b_rel 01
;*l0002!rxthreadlist!!2 gpr_a_rel 08
;*l0002!rxthreadlist!!3 gpr_b_rel 0C
*l0002!rxthreadlist gpr_b_rel 0C
;*l0003!refcnt!!2 gpr_b_rel 00
*l0003!refcnt gpr_b_rel 00
;*l0003!ind_ref_data!!2 gpr_a_rel 06
;*l0003!ind_ref_data!!3 gpr_b_rel 07
*l0003!ind_ref_data gpr_b_rel 07
*$l0003!sram_data sram_rel 01 0 both 1 0x0
*l0004!rbufoffset gpr_b_rel 08
*l0005!pkt_buff_addr gpr_b_rel 01
;*l0005!rel!!2 gpr_b_rel 09
*l0005!rel gpr_b_rel 09
*l0005!freebuffer gpr_b_rel 02
*l0006!rbuf_elem_done_data gpr_b_rel 0F
*l0000!dram_sig signal 02 0
*l0000!sram_sig signal 01 0
*l0000!sram_sig!!2 signal 01 0
*l0000!scratch_sig signal 01 0
*l0000!inter_me_sig signal 0F 0
*l0000!same_me_sig signal 0E 0
*l0000!rx_sig signal 01 0
.%type R
.%type SI
.%scope global
.%var l0006!rbuf_elem_done_data 0 R
.%liverange 0 B15 74:75
.%liverange 0 ~B15 36:73 76:76
.%var l0005!freebuffer 0 R
.%liverange 0 B2 58:75
.%liverange 0 ~B2 36:57 76:76
.%var l0005!rel 0 R
.%liverange 0 B9 59:75
.%liverange 0 ~B9 36:58 76:76
.%var l0005!pkt_buff_addr 0 R
.%liverange 0 B1 61:75
.%liverange 0 ~B1 36:60 76:76
.%var l0004!rbufoffset 0 R
.%liverange 0 B8 52:75
.%liverange 0 ~B8 36:51 76:76
.%var $l0003!sram_data 0 R
.%liverange 0 $W1 54:75
.%liverange 0 ~$W1 36:53 76:76
.%liverange 0 $R1 77:77
.%var l0003!ind_ref_data 0 R
.%liverange 0 B7 53:55 62:75
.%liverange 0 ~B7 36:52 76:76
.%liverange 0 A6 56:61
.%var l0003!refcnt 0 R
.%liverange 0 B0 47:75
.%liverange 0 ~B0 36:46 76:76
.%var l0002!rxthreadlist 0 R
.%liverange 0 B12 23:23 25:76
.%liverange 0 A8 24:24
.%var l0001!temp 0 R
.%liverange 0 B1 2:35
.%liverange 0 ~B1 36:60 76:76
.%var @l0000!drampacketbase 0 R
.%liverange 0 @A21 0:76
.%var @l0000!sramdescbase 0 R
.%liverange 0 @A5 0:76
.%var $l0000!ring_data 0 R
.%liverange 0 $W0 66:75
.%liverange 0 ~$W0 36:65 76:76
.%liverange 0 $R0 77:77
.%var $l0000!sr0 0 R
.%liverange 0 $W0 77:77
.%liverange 0 $R0 43:75
.%liverange 0 ~$R0 36:42 76:76
.%var l0000!rx_port_num 0 R
.%liverange 0 B6 46:75
.%liverange 0 ~B6 36:45 76:76
.%var l0000!bytecnt 0 R
.%liverange 0 A4 45:75
.%liverange 0 ~A4 36:44 76:76
.%var l0000!elem 0 R
.%liverange 0 A3 44:75
.%liverange 0 ~A3 36:43 76:76
.%var l0000!null 0 R
.%liverange 0 B14 40:76
.%liverange 0 ~B14 36:39
.%var l0000!rx_thd_freelist 0 R
.%liverange 0 B5 7:7 11:11 15:15 17:76
.%var l0000!rbuf_elem_done 0 R
.%liverange 0 B11 22:76
.%var l0000!rbuf_base 0 R
.%liverange 0 A2 21:76
.%var $l0000!transferreg01 0 R
.%liverange 0 $W2 77:77
.%liverange 0 $R2 77:77
.%var $l0000!transferreg00 0 R
.%liverange 0 $W1 0:35
.%liverange 0 ~$W1 36:53 76:76
.%liverange 0 $R1 0:76
.%var l0000!rxconfigdata 0 R
.%liverange 0 B13 26:26
.%liverange 0 A1 27:76
.%var l0000!ring 0 R
.%liverange 0 B4 18:76
.%var l0000!t0 0 R
.%liverange 0 B3 20:76
.%var l0000!sram_channel_number 0 R
.%liverange 0 A0 19:76
.%var l0000!cur_ctx 0 R
.%liverange 0 B10 4:76
.%var l0000!cur_me 0 R
.%liverange 0 A7 3:76
.%var l0000!dram_sig 1 R
.%liverange 0 D2 36:61 63:76
.%var l0000!sram_sig 1 R
.%liverange 0 G1 43:56 64:66
.%var l0000!scratch_sig 1 R
.%liverange 0 G1 73:76
.%var l0000!inter_me_sig 1 R
.%liverange 0 G15 0:33
.%var l0000!same_me_sig 1 R
.%liverange 0 G14 34:39 41:76
.%var l0000!rx_sig 1 R
.%liverange 0 G1 36:39
.%scope end
.0 FC044C0000 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 47 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg l0000!cur_me l0000!cur_ctx
	.%line 48 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg l0000!sram_channel_number l0000!t0
	.%line 49 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg l0000!ring
	.%line 50 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg l0000!rxconfigdata
	.%line 51 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg $l0000!transferreg00 $l0000!transferreg01
	.%line 52 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg l0000!rbuf_base l0000!rbuf_elem_done l0000!rx_thd_freelist
	.%line 53 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg l0000!null l0000!elem l0000!bytecnt l0000!rx_port_num
	.%line 55 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg $l0000!sr0
	.%line 56 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg $l0000!ring_data
	.%line 57 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.reg @l0000!sramdescbase @l0000!drampacketbase @l0000!half_duplex
	.%line 59 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.sig l0000!rx_sig l0000!same_me_sig l0000!inter_me_sig
	.%line 60 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.sig l0000!scratch_sig l0000!sram_sig l0000!dram_sig
	.%line 62 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.xfer_order $l0000!transferreg00 $l0000!transferreg01
	.%line 64 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.set $l0000!transferreg00
	.%line 66 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.set_sig l0000!inter_me_sig
	.%line 68 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.addr l0000!same_me_sig 14
	.%line 69 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.addr l0000!inter_me_sig 15
	.%line 75 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.begin
	.%line 76 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
		.reg l0001!temp
	.%line 77 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 1
		local_csr_rd[active_ctx_sts]
.1 F000000700 common_code
	.%line 78 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 0
		immed[l0001!temp, 0]
.2 843070053F common_code
	.%line 79 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
		alu_shf[l0000!cur_me, 0x1f, and, l0001!temp, >>3]
.3 B400A00707 common_code
	.%line 80 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
		alu[l0000!cur_ctx, 0x7, and, l0001!temp]
.4 A0700C0007 common_code
	.%line 81 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
	.end
	.%line 83 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
		.if (cur_me == 0)
	.%line 83 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
		alu[--,--,b,l0000!cur_me]
.5 D802000101 common_code
	.%line 83 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0 8
		bne[l000_01#]
.6 F000001730 common_code
	.%line 84 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
			immed[l0000!rx_thd_freelist, 0x0030]
.7 D804400018 common_code
	.%line 85 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
		.elif (cur_me == 1)
	.%line 85 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0 17
		br[l000_end#]
.8 AAB00C0407 common_code
	.%line 85 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
		l000_01#: 
		alu[--,l0000!cur_me,-,1]
.9 D803000101 common_code
	.%line 85 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0 12
		bne[l000_02#]
.10 F000001734 common_code
	.%line 86 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
			immed[l0000!rx_thd_freelist, 0x0034]
.11 D804400018 common_code
	.%line 87 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
		.elif (cur_me == 2)
	.%line 87 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0 17
		br[l000_end#]
.12 AAB00C0807 common_code
	.%line 87 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
		l000_02#: 
		alu[--,l0000!cur_me,-,2]
.13 D804000101 common_code
	.%line 87 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0 16
		bne[l000_03#]
.14 F000001738 common_code
	.%line 88 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0
			immed[l0000!rx_thd_freelist, 0x0038]
.15 D804400018 common_code
	.%line 89 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bw\line_rate_bw_in_rx.uc" 1 0