line_rate_bw.h

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/*---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 * --------------------------------------------------------------------------
 */
#ifndef LINE_RATE_BW_COMMON_H

#define LINE_RATE_BW_COMMON_H

#include "common_uc.h"

#define IN_RX_PHY						MSF_SINGLE_PHY
#define IN_RX_WIDTH						MSF_WIDTH_4x8
#define IN_RX_ENABLE_MASK				0xF
#define IN_RX_MODE						MSF_POS_UTOPIA
#define IN_RX_ELEMENT_SIZE				MSF_ELEMENTSIZE_128
#define IN_RBUF_ELEM_COUNT				(1 << (7 - IN_RX_ELEMENT_SIZE))
#define IN_RBUF_ADDR_SHF				(6 + IN_RX_ELEMENT_SIZE)
#define IN_RX_ELEMENTSIZE_BYTE			(1 << IN_RBUF_ADDR_SHF)

#define IN_SRAM_DESC_BASE				0x200000		// 2 Meg onwards
#define IN_DRAM_PCKT_BASE				0x1000000		// 16 Meg onwards

#define IN_ME_RX_0						0
#define IN_ME_RX_1						1
#define IN_ME_RX_2						2
#define IN_ME_RX_3						3
#define IN_ME_TX						16
#define IN_SIG_THD_NUM					0
#define IN_SAME_ME_SIG_NUM				14
#define IN_INTER_ME_SIG_NUM				15

#define IN_TX_PHY						MSF_SINGLE_PHY
#define IN_TX_WIDTH						MSF_WIDTH_1x32
#define IN_TX_ENABLE_MASK				0x1
#define IN_TX_MODE						MSF_CSIX
#define IN_TX_ELEMENTSIZE				MSF_ELEMENTSIZE_128
#define IN_TBUF_ELEM_COUNT				(((1 << (7 - IN_TX_ELEMENTSIZE)) >> 2) * 3)	// Tot. elements
#define IN_TBUF_ADDR_SHF				(6 + IN_TX_ELEMENTSIZE)
#define IN_TX_ELEMENTSIZE_BYTE			(1 << IN_TBUF_ADDR_SHF)
#define IN_TBUF_CTRL_ADDR_SHF			(3 + IN_TX_ELEMENTSIZE)

#define EG_RX_PHY						MSF_SINGLE_PHY
#define EG_RX_WIDTH						MSF_WIDTH_1x32
#define EG_RX_ENABLE_MASK 				0x1
#define EG_RX_MODE						MSF_CSIX
#define EG_RX_ELEMENT_SIZE				MSF_ELEMENTSIZE_128
#define EG_RBUF_ELEM_COUNT				(((1 << (7 - EG_RX_ELEMENT_SIZE)) >> 2) * 3)	// Tot. elements
#define EG_RBUF_ADDR_SHF				(6 + EG_RX_ELEMENT_SIZE)
#define EG_RX_ELEMENTSIZE_BYTE			(1 << EG_RBUF_ADDR_SHF)

#define EG_TX_PHY						MSF_SINGLE_PHY
#define EG_TX_WIDTH						MSF_WIDTH_4x8
#define EG_TX_ENABLE_MASK				0xF
#define EG_TX_MODE						MSF_POS_UTOPIA
#define EG_TX_ELEMENTSIZE				MSF_ELEMENTSIZE_128
#define EG_TBUF_ELEM_COUNT				(1 << (7 - EG_TX_ELEMENTSIZE))	// Tot. elements
#define EG_TBUF_ELEM_COUNT_PER_PORT		(EG_TBUF_ELEM_COUNT >> 2)
#define EG_TBUF_ADDR_SHF				(6 + EG_TX_ELEMENTSIZE)
#define EG_TX_ELEMENTSIZE_BYTE			(1 << EG_TBUF_ADDR_SHF)
#define EG_TBUF_CTRL_ADDR_SHF			3
#define EG_TBUF_ELEM_COUNT_MASK			(EG_TBUF_ELEM_COUNT - 1)	// Tot. elements
#define EG_TBUF_ELEM_COUNT_PER_PORT_MASK (EG_TBUF_ELEM_COUNT_PER_PORT - 1)

#define EG_SRAM_DESC_BASE				0x200000		// 2 Meg onwards
#define EG_DRAM_PCKT_BASE				0x1000000		// 16 Meg onwards

#define EG_ME_NUMBER_RX					16
#define EG_ME_NUMBER_TX_0				0
#define EG_ME_NUMBER_TX_1				1
#define EG_ME_NUMBER_TX_2				2
#define EG_ME_NUMBER_TX_3				3
#define EG_SIG_THD_NUM					0
#define EG_SAME_ME_SIG_NUM				14
#define EG_INTER_ME_SIG_NUM				15

#define EXT_HDR							0

#define NUMBER_OF_PORTS					4
#define PORT_0							0
#define PORT_1							1
#define PORT_2							2
#define PORT_3							3

#define TX_CONTROL_EOP					(1 << 8)
#define TX_CONTROL_SOP					(1 << 9)

#define	TBUF_ELE_BITS_MASK 				0xFF
// definition of the threshold to wait to avoid overwriting existing mpackets
// not transmitted out of tbuf yet, 
#define TBUF_WAIT_THRESHOLD				40

#endif		//#ifndef LINE_RATE_BW_COMMON_H