📄 media_lb_bw_on_sf_iface_rx.uc
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/* media_lb_pl_on_sf_iface_rx.uc
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, April, 2002
* revisions: cmah1, March 11, 2003
*
*
* --------------------------------------------------------------------------
*/
#include "common_uc.h"
#define RX_SINGLE_PHY MSF_SINGLE_PHY
#define RX_WIDTH MSF_WIDTH_4x8
#define RX_ENABLE_MASK 0xF
#define RX_MODE MSF_POS_UTOPIA
#define RX_ELEMENTSIZE MSF_ELEMENTSIZE_128
#define RBUF_ELEM_COUNT (1 << (7 - RX_ELEMENTSIZE))
#define RBUF_ADDR_SHF (6 + RX_ELEMENTSIZE)
#define RX_ELEMENT_SIZE_BYTE (1 << RBUF_ADDR_SHF)
#define ME_NUM_RX 0
#define RX_TRANSFER_THREAD &$TransferReg00
#define RX_SIGNAL_THREAD &rx_sig_thd
#define INTERTHD_SIG_NUM 15
#define DRAM_PCKT_BASE 0x1000000
.reg $TransferReg00 $TransferReg01
.reg RxThreadList bytecnt elem error rx_channel_num
.reg cur_ctx
.reg @packet_count
.reg RxConfigData
.reg rbuf ring_num
.reg MsfAddress ThreadFreelist_Addr ElementDone_Addr
.reg dramPacketBase
.reg put_ring_num rx_count_ring_num
.sig msf_sig sig_dram_xfer1
.sig rx_sig_thd interthd_sig
.xfer_order $TransferReg00 $TransferReg01
.addr interthd_sig INTERTHD_SIG_NUM
.set $TransferReg00
.set_sig interthd_sig
Init_Value#:
br!=ctx[0, not_ctx_0#]
immed[ThreadFreelist_Addr, RX_THREAD_FREELIST_0]
br[cont_init1#]
not_ctx_0#:
br!=ctx[1, not_ctx_1#]
immed[ThreadFreelist_Addr, RX_THREAD_FREELIST_1]
br[cont_init1#]
not_ctx_1#:
br!=ctx[2, not_ctx_2#]
immed[ThreadFreelist_Addr, RX_THREAD_FREELIST_2]
br[cont_init1#]
not_ctx_2#:
br!=ctx[3, not_ctx_3#]
immed[ThreadFreelist_Addr, RX_THREAD_FREELIST_3]
br[cont_init1#]
not_ctx_3#:
ctx_arb[kill]
cont_init1#:
.begin
.reg temp cur_me
local_csr_rd[ACTIVE_CTX_STS]
immed[temp, 0]
alu[cur_me, MASK_4BIT, AND, temp, >>3] // Extract the current ME number
alu[cur_ctx, MASK_3BIT, AND, temp] // Extract the current context number
alu[ring_num, --, B, cur_ctx, <<2] // ring number in a register
immed[RxThreadList, (RX_SIGNAL_THREAD << 12)]
alu[RxThreadList, RxThreadList, OR, cur_me, <<7]
alu[RxThreadList, RxThreadList, OR, cur_ctx, <<4]
alu[RxConfigData, RxThreadList, OR , RX_TRANSFER_THREAD]
alu[RxConfigData, --, B, RxConfigData, <<16]
.end
immed[dramPacketBase, (DRAM_PCKT_BASE & MASK_16BIT)]
immed_w1[dramPacketBase, ((DRAM_PCKT_BASE >> 16) & MASK_16BIT)]
alu[dramPacketBase, dramPacketBase, OR, cur_ctx, <<RBUF_ADDR_SHF]
alu[put_ring_num , --, B, cur_ctx, <<2]
alu[rx_count_ring_num , --, B, RING_4, <<2]
immed[ElementDone_Addr, RBUF_ELEMENT_DONE]
immed[rbuf, RBUF_TBUF ]
br=ctx[0, cont_init2#]
ctx_arb[interthd_sig]
br[ReceivePacket#]
cont_init2#:
immed[@packet_count, 0]
//****************************************************
// Configure RX/TX Control
//****************************************************
.begin
.reg RxConfigData0 $RxConfigData0
immed[RxConfigData0, ((0<<9) | (RX_ELEMENTSIZE << 2))]
immed_w1[RxConfigData0, ((RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
alu[$RxConfigData0, --, B, RxConfigData0]
immed[MsfAddress, MSF_RX_CONTROL]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//******************************************************
// Initialize RBUF Freelist to add elements to the list
//******************************************************
.begin
.reg temp_reg temp
immed[temp_reg, 0]
init_RBUF#:
alu[temp, --, B, temp_reg, <<16]
msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
alu[temp_reg, temp_reg, +, 1]
alu[--, RBUF_ELEM_COUNT, -, temp_reg]
bne[init_RBUF#]
.end
//******************************************************
// Configure RX UP Control CSRs
//******************************************************
.begin
.reg RxUPControl $RxConfigData0
// immed[RxUPControl, (UP_CTRL_PP_MODE_PLONE | UP_CTRL_CP_MODE | UP_CTRL_PARITY_ODD | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
immed[RxUPControl, (UP_CTRL_PP_MODE | UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
alu[$RxConfigData0, --, B, RxUPControl]
immed[MsfAddress, RX_UP_CONTROL_0]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, RX_UP_CONTROL_1]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, RX_UP_CONTROL_2]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, RX_UP_CONTROL_3]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//****************************************************
// Configure RX/TX Control
//****************************************************
.begin
.reg RxConfigData0 $RxConfigData0
immed[RxConfigData0, ((0<<9) | (RX_ELEMENTSIZE << 2))]
immed_w1[RxConfigData0, ((RX_ENABLE_MASK << 12) | (RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
alu[$RxConfigData0, --, B, RxConfigData0]
immed[MsfAddress, MSF_RX_CONTROL]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.end
//**************************************************
// Configure Scratch Ring
//**************************************************
.begin
.reg $scratch_base $scratch_head $scratch_tail
.sig scratch_sig1 scratch_sig2 scratch_sig3
immed[$scratch_head,0]
immed[$scratch_tail,0]
alu[$scratch_base, --, B, 0] // Use ring size of 128 lw and base 0x0
cap[write,$scratch_base,SCRATCH_RING_BASE_0],sig_done[scratch_sig1]
cap[write,$scratch_head,SCRATCH_RING_HEAD_0],sig_done[scratch_sig2]
cap[write,$scratch_tail,SCRATCH_RING_TAIL_0],sig_done[scratch_sig3]
ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
alu[$scratch_base, --, B, 1, <<9] // Use ring size of 128 lw and base 0x200
cap[write,$scratch_base,SCRATCH_RING_BASE_1],sig_done[scratch_sig1]
cap[write,$scratch_head,SCRATCH_RING_HEAD_1],sig_done[scratch_sig2]
cap[write,$scratch_tail,SCRATCH_RING_TAIL_1],sig_done[scratch_sig3]
ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
alu[$scratch_base, --, B, 2, <<9] // Use ring size of 128 lw and base 0x400
cap[write,$scratch_base,SCRATCH_RING_BASE_2],sig_done[scratch_sig1]
cap[write,$scratch_head,SCRATCH_RING_HEAD_2],sig_done[scratch_sig2]
cap[write,$scratch_tail,SCRATCH_RING_TAIL_2],sig_done[scratch_sig3]
ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
alu[$scratch_base, --, B, 3, <<9] // Use ring size of 128 lw and base 0x600
cap[write,$scratch_base,SCRATCH_RING_BASE_3],sig_done[scratch_sig1]
cap[write,$scratch_head,SCRATCH_RING_HEAD_3],sig_done[scratch_sig2]
cap[write,$scratch_tail,SCRATCH_RING_TAIL_3],sig_done[scratch_sig3]
ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
alu[$scratch_base, --, B, 4, <<9] // Use ring size of 128 lw and base 0x800
cap[write,$scratch_base,SCRATCH_RING_BASE_4],sig_done[scratch_sig1]
cap[write,$scratch_head,SCRATCH_RING_HEAD_4],sig_done[scratch_sig2]
cap[write,$scratch_tail,SCRATCH_RING_TAIL_4],sig_done[scratch_sig3]
ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
.end
local_csr_wr[SAME_ME_SIGNAL, ((INTERTHD_SIG_NUM << 3) | 1)]
local_csr_wr[SAME_ME_SIGNAL, ((INTERTHD_SIG_NUM << 3) | 2)]
local_csr_wr[SAME_ME_SIGNAL, ((INTERTHD_SIG_NUM << 3) | 3)]
//********************************************************
// Start of Test
//********************************************************
ReceivePacket#:
.set_sig rx_sig_thd
msf[fast_wr, --, ThreadFreelist_Addr, RxConfigData] // add thread to freelist
ctx_arb[rx_sig_thd]
// RSW should be in xfer register
// Transfer RBUF data to sram_in transfer registers
//***************************************
// Extract RSW 7 cycles
//****************************************
RSW#:
alu[elem, --, B, $TransferReg00, >>24] // Get element number
alu[bytecnt, 0xFF, AND, $TransferReg00, >>16] // Extract byte count
alu[error, 0xF, AND, $TransferReg00, >>10] // Extract error information
alu[rx_channel_num, 0xf, AND, $TransferReg00] // Extract channel
//*********************************
// Transfer from ME to DRAM
//*********************************
.begin
.reg pkt_buff_addr rel RBufOffset refcnt temp
alu[refcnt, --, B, bytecnt, >>3]
alu[--, bytecnt, AND, 0x7]
bne[set_refcnt_overwrite_bit#]
alu[refcnt, refcnt, -, 1]
set_refcnt_overwrite_bit#:
alu[refcnt, refcnt, OR, 1, <<4] // Set the overwrite bit for refcnt
alu[RBufOffset, --, B, elem, <<7] // 128B
alu[temp, RBuf, +, RBufOffset]
alu[temp, 16, OR, temp, <<5] // shift rbuf addr and set the overwrite bit
alu[temp, temp, OR, refcnt, <<21] // shift refcnt and add for indirect ref
dram[rbuf_rd, --, dramPacketBase, 0, 8], indirect_ref, sig_done[sig_dram_xfer1]
ctx_arb[sig_dram_xfer1]
.end
//**************************************************************
// Free up Element by writing to RBUF_Element_Done
//**************************************************************
.begin
.reg $temp0
alu[$temp0, --, B, elem]
msf[write, $temp0, ElementDone_Addr,0, 1], ctx_swap[msf_sig]
.end
/*
//*****************************************************************
// Write to Scratch ring to signal completion to XScale code
//*****************************************************************
.begin
.reg $scratch_data temp
.sig scratch_sig
alu[temp, bytecnt, OR, error, <<16]
alu[$scratch_data, temp, OR, rx_channel_num, <<24]
scratch[put, $scratch_data, ring_num, 0, 1], ctx_swap[scratch_sig]
alu[$scratch_data, --, B, dramPacketBase]
scratch[put, $scratch_data, ring_num, 0, 1], ctx_swap[scratch_sig]
.end
*/
alu[@packet_count, @packet_count, +, 1]
.begin
.reg $scratch_packet_count
.sig scratch_sig
alu[$scratch_packet_count, bytecnt, OR, rx_channel_num, <<16]
scratch[put, $scratch_packet_count, rx_count_ring_num, 0, 1], ctx_swap[scratch_sig]
.end
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