sys_loopback_bw_2_eg_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:01:46 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:cont_comp_tbuf_tx_sequnce# 78
:init# 2
:init_msf# 31
:l000_01# 15
:l000_02# 20
:l000_03# 25
:l000_end# 27
:msf_init_done# 60
:next_packet# 67
:read_tx_sequence_loop# 71
*-- no_destination 0
*l0000!cur_me gpr_b_rel 03
;*l0000!msfaddress!!2 gpr_b_rel 04
;*l0000!msfaddress!!3 gpr_b_rel 04
;*l0000!msfaddress!!4 gpr_b_rel 04
;*l0000!msfaddress!!5 gpr_b_rel 04
;*l0000!msfaddress!!6 gpr_b_rel 04
;*l0000!msfaddress!!7 gpr_a_rel 03
;*l0000!msfaddress!!8 gpr_a_rel 03
*l0000!msfaddress gpr_b_rel 04
*l0000!txsequenceaddr gpr_b_rel 00
*l0000!total_packets_tx gpr_b_rel 0D
;*l0000!future_count_value!!2 gpr_b_rel 05
*l0000!future_count_value gpr_a_rel 00
*l0000!future_count_incr gpr_b_rel 01
*l0000!byte_count gpr_a_rel 01
;*l0000!txconfigdata0!!2 gpr_a_rel 04
;*l0000!txconfigdata0!!3 gpr_a_rel 04
*l0000!txconfigdata0 gpr_a_rel 04
*$l0000!txconfigdata0 sram_rel 00 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x13
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x13
;*l0000!tbuf_element!!2 gpr_b_rel 06
*l0000!tbuf_element gpr_a_rel 02
*l0000!base_element_for_port gpr_b_rel 02
*l0001!temp gpr_b_rel 0E
;*l0002!temp!!2 gpr_b_rel 07
;*l0002!temp!!3 gpr_b_rel 07
*l0002!temp gpr_b_rel 07
*$l0003!temp_reg_val sram_rel 00 0 both 1 0x0
;*l0004!result!!2 gpr_b_rel 08
*l0004!result gpr_a_rel 05
*l0004!tmp_val gpr_b_rel 09
*l0004!tmp_tbuf gpr_b_rel 0A
*$l0004!txsequencedata sram_rel 00 0 both 1 0x0
*l0005!temp gpr_b_rel 0B
*l0005!cur_tbuf_elem gpr_b_rel 0C
*l0003!cap_sig signal 01 0
*l0000!inter_me_sig signal 0F 0
*l0000!future_count_sig signal 01 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!8 signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var l0005!cur_tbuf_elem 0 R
.%liverange 0 B12 82:91
.%liverange 0 ~B12 67:81
.%var l0005!temp 0 R
.%liverange 0 B11 85:91
.%liverange 0 ~B11 67:84
.%var $l0004!txsequencedata 0 R
.%liverange 0 $W0 92:92
.%liverange 0 $R0 72:91
.%liverange 0 ~$R0 67:71
.%var l0004!tmp_tbuf 0 R
.%liverange 0 B10 77:91
.%liverange 0 ~B10 67:76
.%var l0004!tmp_val 0 R
.%liverange 0 B9 74:91
.%liverange 0 ~B9 67:73
.%var l0004!result 0 R
.%liverange 0 A5 73:78
.%liverange 0 B8 79:91
.%liverange 0 ~B8 67:72
.%var $l0003!temp_reg_val 0 R
.%liverange 0 $W0 92:92
.%liverange 0 $R0 65:66
.%liverange 0 ~$R0 67:71
.%var l0002!temp 0 R
.%liverange 0 B7 52:59
.%liverange 0 ~B7 60:91
.%var l0001!temp 0 R
.%liverange 0 B14 4:91
.%var l0000!base_element_for_port 0 R
.%liverange 0 B2 13:14 18:19 23:24 26:91
.%var l0000!tbuf_element 0 R
.%liverange 0 A2 7:89 91:91
.%liverange 0 B6 90:90
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 87:91
.%liverange 0 ~$W1 67:86
.%liverange 0 $R1 92:92
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 86:91
.%liverange 0 ~$W0 67:85
.%liverange 0 $R0 92:92
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W0 35:59
.%liverange 0 ~$W0 60:85
.%liverange 0 $R0 92:92
.%var l0000!txconfigdata0 0 R
.%liverange 0 A4 33:59
.%liverange 0 ~A4 60:91
.%var l0000!byte_count 0 R
.%liverange 0 A1 8:91
.%var l0000!future_count_incr 0 R
.%liverange 0 B1 10:91
.%var l0000!future_count_value 0 R
.%liverange 0 A0 9:68 70:91
.%liverange 0 B5 69:69
.%var l0000!total_packets_tx 0 R
.%liverange 0 B13 6:91
.%var l0000!txsequenceaddr 0 R
.%liverange 0 B0 14:14 19:19 24:24 27:91
.%var l0000!msfaddress 0 R
.%liverange 0 B4 32:59
.%liverange 0 ~B4 60:82
.%liverange 0 A3 83:91
.%liverange 0 ~A3 67:82
.%var l0000!cur_me 0 R
.%liverange 0 B3 5:91
.%var l0003!cap_sig 1 R
.%liverange 0 G1 65:65
.%var l0000!inter_me_sig 1 R
.%liverange 0 G15 0:0 2:30
.%var l0000!future_count_sig 1 R
.%liverange 0 G1 81:88
.%var l0000!msf_sig 1 R
.%liverange 0 G1 36:36 40:40 42:42 44:44 46:46 51:51 72:72 89:89
.%scope end
.0 D800800010 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 77 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.reg l0000!cur_me
	.%line 78 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.reg l0000!msfaddress l0000!txsequenceaddr l0000!total_packets_tx
	.%line 79 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.reg l0000!future_count_value l0000!future_count_incr
	.%line 80 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.reg l0000!byte_count
	.%line 81 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.reg l0000!txconfigdata0
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.reg $l0000!txconfigdata0
	.%line 83 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.reg l0000!tbuf_element l0000!base_element_for_port
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.sig l0000!msf_sig l0000!future_count_sig l0000!inter_me_sig
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.xfer_order $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.addr l0000!inter_me_sig 15
	.%line 91 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.set_sig l0000!inter_me_sig
	.%line 92 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0 2
	br=ctx[0, init#]
.1 E000010000 common_code
	.%line 93 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	ctx_arb[kill], any
.2 FC044C0000 common_code
	.%line 96 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.begin
	.%line 97 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		.reg l0001!temp
	.%line 95 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 1
	init#:
	.%line 98 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 1
		local_csr_rd[active_ctx_sts]
.3 F000003B00 common_code
	.%line 99 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 0
		immed[l0001!temp, 0]
.4 943030393F common_code
	.%line 100 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		alu_shf[l0000!cur_me, 0x1f, and, l0001!temp, >>3]
.5 F000003700 common_code
	.%line 101 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.end
	.%line 103 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!total_packets_tx, 0]
.6 F0000C0002 common_code
	.%line 104 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!tbuf_element, 0]
.7 F0000CC001 common_code
	.%line 105 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!byte_count, 48]
.8 F0000C0000 common_code
	.%line 106 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!future_count_value, 0]
.9 F000000716 common_code
	.%line 118 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!future_count_incr, 22]
.10 A030000C00 common_code
	.%line 120 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.if (cur_me == 0)
	.%line 120 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	alu[--,--,b,l0000!cur_me]
.11 D803C00101 common_code
	.%line 120 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0 15
	bne[l000_01#]
.12 F000000B00 common_code
	.%line 121 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!base_element_for_port, 0]
.13 F000000360 common_code
	.%line 122 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!txsequenceaddr, 0x0060]
.14 D806C00018 common_code
	.%line 123 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.elif (cur_me == 1)
	.%line 123 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0 27
	br[l000_end#]
.15 AAF0000F01 common_code
	.%line 123 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	l000_01#: 
	alu[--,l0000!cur_me,-,1]
.16 D805000101 common_code
	.%line 123 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0 20
	bne[l000_02#]
.17 F000000B10 common_code
	.%line 125 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!base_element_for_port, 16]
.18 F000000364 common_code
	.%line 126 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!txsequenceaddr, 0x0064]
.19 D806C00018 common_code
	.%line 127 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	.elif (cur_me == 2)
	.%line 127 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0 27
	br[l000_end#]
.20 AAF0000F02 common_code
	.%line 127 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
	l000_02#: 
	alu[--,l0000!cur_me,-,2]
.21 D806400101 common_code
	.%line 127 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0 25
	bne[l000_03#]
.22 F000000B20 common_code
	.%line 129 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!base_element_for_port, 32]
.23 F000000368 common_code
	.%line 130 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_eg_tx.uc" 1 0
		immed[l0000!txsequenceaddr, 0x0068]