sys_loopback_bw_2_in_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 12:01:46 2004

.cpu_version 0x00000002 1 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:check_ring_full# 67
:freelist_addr_done# 17
:init_done# 39
:init_thread0_only# 34
:l000_01# 8
:l000_02# 12
:l000_03# 16
:l000_end# 17
:l001_01# 26
:l001_end# 27
:next_packet# 72
:null# 72
:receivenextpacket# 41
:rsw# 43
:set_refcnt_overwrite_bit# 53
:startreceive# 41
:wait_for_inter_me_sig# 38
*-- no_destination 0
*l0000!cur_me gpr_a_rel 07
*l0000!cur_ctx gpr_a_rel 08
*l0000!same_me_sig_info gpr_b_rel 0A
*l0000!sram_channel_number gpr_a_rel 00
*l0000!t0 gpr_b_rel 02
*l0000!ring gpr_b_rel 03
;*l0000!rxconfigdata!!2 gpr_a_rel 01
*l0000!rxconfigdata gpr_b_rel 0B
*$l0000!transferreg00 sram_rel 01 0 both 2 0x20
*$l0000!transferreg01 sram_rel 02 0 both 1 0x20
*l0000!rbuf_base gpr_a_rel 02
*l0000!rbuf_elem_done gpr_b_rel 0C
*l0000!rx_thd_freelist gpr_b_rel 04
*l0000!null gpr_b_rel 0D
*l0000!elem gpr_a_rel 03
*l0000!bytecnt gpr_a_rel 04
*l0000!rx_port_num gpr_b_rel 05
*$l0000!sr0 sram_rel 00 0 both 1 0x0
*$l0000!ring_data sram_rel 00 0 both 1 0x0
*@l0000!sramdescbase gpr_a_abs 05
*@l0000!drampacketbase gpr_a_abs 15
*l0001!temp gpr_b_rel 00
;*l0002!rxthreadlist!!2 gpr_b_rel 0E
;*l0002!rxthreadlist!!3 gpr_b_rel 0E
*l0002!rxthreadlist gpr_b_rel 0E
;*l0003!refcnt!!2 gpr_a_rel 06
*l0003!refcnt gpr_b_rel 08
;*l0003!ind_ref_data!!2 gpr_b_rel 06
;*l0003!ind_ref_data!!3 gpr_b_rel 06
*l0003!ind_ref_data gpr_b_rel 06
*l0004!rbufoffset gpr_b_rel 09
*l0005!pkt_buff_addr gpr_b_rel 00
;*l0005!rel!!2 gpr_b_rel 07
*l0005!rel gpr_b_rel 07
*l0005!freebuffer gpr_b_rel 01
*$l0005!sram_data sram_rel 01 0 both 1 0x0
*l0006!rbuf_elem_done_data gpr_b_rel 0F
*l0000!dram_sig signal 04 0
*l0000!sram_sig signal 02 0
*l0000!sram_sig!!2 signal 02 0
*l0000!scratch_sig signal 01 0
*l0000!inter_me_sig signal 0F 0
*l0000!same_me_sig signal 0E 0
*l0000!rx_sig signal 01 0
.%type R
.%type SI
.%scope global
.%var l0006!rbuf_elem_done_data 0 R
.%liverange 0 B15 71:71
.%liverange 0 ~B15 41:70 72:72
.%var $l0005!sram_data 0 R
.%liverange 0 $W1 65:71
.%liverange 0 ~$W1 41:64 72:72
.%liverange 0 $R1 73:73
.%var l0005!freebuffer 0 R
.%liverange 0 B1 59:71
.%liverange 0 ~B1 41:58 72:72
.%var l0005!rel 0 R
.%liverange 0 B7 60:71
.%liverange 0 ~B7 41:59 72:72
.%var l0005!pkt_buff_addr 0 R
.%liverange 0 B0 62:71
.%liverange 0 ~B0 41:61 72:72
.%var l0004!rbufoffset 0 R
.%liverange 0 B9 55:71
.%liverange 0 ~B9 41:54 72:72
.%var l0003!ind_ref_data 0 R
.%liverange 0 B6 56:71
.%liverange 0 ~B6 41:55 72:72
.%var l0003!refcnt 0 R
.%liverange 0 B8 50:53
.%liverange 0 A6 54:71
.%liverange 0 ~A6 41:49 72:72
.%var l0002!rxthreadlist 0 R
.%liverange 0 B14 28:72
.%var l0001!temp 0 R
.%liverange 0 B0 2:40
.%liverange 0 ~B0 41:61 72:72
.%var @l0000!drampacketbase 0 R
.%liverange 0 @A21 0:72
.%var @l0000!sramdescbase 0 R
.%liverange 0 @A5 0:72
.%var $l0000!ring_data 0 R
.%liverange 0 $W0 67:71
.%liverange 0 ~$W0 41:66 72:72
.%liverange 0 $R0 73:73
.%var $l0000!sr0 0 R
.%liverange 0 $W0 73:73
.%liverange 0 $R0 46:71
.%liverange 0 ~$R0 41:45 72:72
.%var l0000!rx_port_num 0 R
.%liverange 0 B5 49:71
.%liverange 0 ~B5 41:48 72:72
.%var l0000!bytecnt 0 R
.%liverange 0 A4 48:71
.%liverange 0 ~A4 41:47 72:72
.%var l0000!elem 0 R
.%liverange 0 A3 47:71
.%liverange 0 ~A3 41:46 72:72
.%var l0000!null 0 R
.%liverange 0 B13 44:72
.%liverange 0 ~B13 41:43
.%var l0000!rx_thd_freelist 0 R
.%liverange 0 B4 7:7 11:11 15:15 17:72
.%var l0000!rbuf_elem_done 0 R
.%liverange 0 B12 22:72
.%var l0000!rbuf_base 0 R
.%liverange 0 A2 21:72
.%var $l0000!transferreg01 0 R
.%liverange 0 $W2 73:73
.%liverange 0 $R2 73:73
.%var $l0000!transferreg00 0 R
.%liverange 0 $W1 0:40
.%liverange 0 ~$W1 41:64 72:72
.%liverange 0 $R1 0:72
.%var l0000!rxconfigdata 0 R
.%liverange 0 B11 31:31
.%liverange 0 A1 32:72
.%var l0000!ring 0 R
.%liverange 0 B3 18:72
.%var l0000!t0 0 R
.%liverange 0 B2 20:72
.%var l0000!sram_channel_number 0 R
.%liverange 0 A0 19:72
.%var l0000!same_me_sig_info 0 R
.%liverange 0 B10 25:25 27:72
.%var l0000!cur_ctx 0 R
.%liverange 0 A8 4:72
.%var l0000!cur_me 0 R
.%liverange 0 A7 3:72
.%var l0000!dram_sig 1 R
.%liverange 0 D4 64:70
.%var l0000!sram_sig 1 R
.%liverange 0 G2 46:58 66:70
.%var l0000!scratch_sig 1 R
.%liverange 0 G1 69:70
.%var l0000!inter_me_sig 1 R
.%liverange 0 G15 0:25 27:38
.%var l0000!same_me_sig 1 R
.%liverange 0 G14 39:41
.%var l0000!rx_sig 1 R
.%liverange 0 G1 41:43
.%scope end
.0 FC044C0000 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 49 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg l0000!cur_me l0000!cur_ctx
	.%line 50 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg l0000!same_me_sig_info
	.%line 51 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg l0000!sram_channel_number l0000!t0
	.%line 52 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg l0000!ring
	.%line 53 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg l0000!rxconfigdata
	.%line 54 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg $l0000!transferreg00 $l0000!transferreg01
	.%line 55 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg l0000!rbuf_base l0000!rbuf_elem_done l0000!rx_thd_freelist
	.%line 56 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg l0000!null l0000!elem l0000!bytecnt l0000!rx_port_num
	.%line 58 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg $l0000!sr0
	.%line 59 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg $l0000!ring_data
	.%line 60 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.reg @l0000!sramdescbase @l0000!drampacketbase
	.%line 62 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.sig l0000!rx_sig l0000!same_me_sig l0000!inter_me_sig
	.%line 63 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.sig l0000!scratch_sig l0000!sram_sig l0000!dram_sig
	.%line 65 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.xfer_order $l0000!transferreg00 $l0000!transferreg01
	.%line 67 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.set $l0000!transferreg00
	.%line 69 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.set_sig l0000!inter_me_sig
	.%line 71 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.addr l0000!same_me_sig 14
	.%line 72 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.addr l0000!inter_me_sig 15
	.%line 78 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.begin
	.%line 79 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
		.reg l0001!temp
	.%line 80 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 1
		local_csr_rd[active_ctx_sts]
.1 F000000300 common_code
	.%line 81 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 0
		immed[l0001!temp, 0]
.2 843070013F common_code
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
		alu_shf[l0000!cur_me, 0x1f, and, l0001!temp, >>3]
.3 A400800307 common_code
	.%line 83 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
		alu[l0000!cur_ctx, 0x7, and, l0001!temp]
.4 A0700C0007 common_code
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
	.end
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
		.if (cur_me == 0)
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
		alu[--,--,b,l0000!cur_me]
.5 D802000101 common_code
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0 8
		bne[l000_01#]
.6 F000001330 common_code
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
			immed[l0000!rx_thd_freelist, 0x0030]
.7 D804400018 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
		.elif (cur_me == 1)
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0 17
		br[l000_end#]
.8 AAB00C0407 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
		l000_01#: 
		alu[--,l0000!cur_me,-,1]
.9 D803000101 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0 12
		bne[l000_02#]
.10 F000001334 common_code
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
			immed[l0000!rx_thd_freelist, 0x0034]
.11 D804400018 common_code
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
		.elif (cur_me == 2)
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0 17
		br[l000_end#]
.12 AAB00C0807 common_code
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\sys_loopback_bw_2\sys_loopback_bw_2_in_rx.uc" 1 0
		l000_02#: 
		alu[--,l0000!cur_me,-,2]
.13 D804000101 common_code