dual_bd_eg_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 11:59:07 2004

.cpu_version 0x00000002 16 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:init_all# 2
:init_value# 0
:next_packet# 59
:refcnt_calc_done# 83
:start# 59
:wait_for_packet_data# 60
*-- no_destination 0
;*l0000!msfaddress!!2 gpr_b_rel 08
;*l0000!msfaddress!!3 gpr_b_rel 08
;*l0000!msfaddress!!4 gpr_b_rel 08
;*l0000!msfaddress!!5 gpr_b_rel 08
;*l0000!msfaddress!!6 gpr_b_rel 08
;*l0000!msfaddress!!7 gpr_a_rel 03
;*l0000!msfaddress!!8 gpr_b_rel 08
*l0000!msfaddress gpr_b_rel 08
*l0000!get_ring_num gpr_a_rel 04
*l0000!put_ring_num gpr_b_rel 0C
*@l0000!packet_count gpr_b_abs 00
;*l0000!port_count!!2 gpr_a_rel 05
*l0000!port_count gpr_b_rel 01
*l0000!byte_count gpr_a_rel 00
*l0000!cur_ctx gpr_a_rel 01
;*l0000!txconfigdata0!!2 gpr_b_rel 09
;*l0000!txconfigdata0!!3 gpr_b_rel 09
*l0000!txconfigdata0 gpr_b_rel 09
*$l0000!txconfigdata0 sram_rel 00 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x21
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x21
*l0000!tbuf_element gpr_b_rel 02
*l0000!tbuf_1st_element gpr_b_rel 0D
*l0000!tbuf_mask gpr_b_rel 03
;*l0000!dram_addr!!2 gpr_b_rel 04
*l0000!dram_addr gpr_b_rel 04
*l0000!tbuf gpr_a_rel 02
*l0001!temp gpr_b_rel 0F
*$l0002!scratch_base sram_rel 00 0 both 1 0x0
*$l0002!scratch_head sram_rel 01 0 both 1 0x0
*$l0002!scratch_tail sram_rel 02 0 both 1 0x0
*$l0003!packet_info sram_rel 00 0 both 1 0x0
*l0003!mask gpr_b_rel 0E
;*l0004!tmp_addr!!2 gpr_b_rel 0A
*l0004!tmp_addr gpr_b_rel 0A
*$l0004!tmp_data sram_rel 00 0 both 1 0x0
;*l0005!tbuf_addr!!2 gpr_b_rel 05
;*l0005!tbuf_addr!!3 gpr_a_rel 06
*l0005!tbuf_addr gpr_b_rel 05
;*l0005!refcnt!!2 gpr_b_rel 06
;*l0005!refcnt!!3 gpr_b_rel 06
*l0005!refcnt gpr_b_rel 06
;*l0006!tmp_addr!!2 gpr_b_rel 07
*l0006!tmp_addr gpr_b_rel 07
*$l0006!tmp_data sram_rel 00 0 both 1 0x0
*l0007!temp gpr_b_rel 0B
*l0006!tmp_scratch_sig signal 01 0
*l0004!tmp_scratch_sig signal 01 0
*l0004!tmp_scratch_sig!!2 signal 01 0
*l0003!scratch_sig signal 01 0
*l0002!scratch_sig3 signal 03 0
*l0002!scratch_sig3!!5 signal 03 0
*l0002!scratch_sig3!!4 signal 03 0
*l0002!scratch_sig3!!3 signal 03 0
*l0002!scratch_sig3!!2 signal 03 0
*l0002!scratch_sig2 signal 02 0
*l0002!scratch_sig2!!5 signal 02 0
*l0002!scratch_sig2!!4 signal 02 0
*l0002!scratch_sig2!!3 signal 02 0
*l0002!scratch_sig2!!2 signal 02 0
*l0002!scratch_sig1 signal 01 0
*l0002!scratch_sig1!!5 signal 01 0
*l0002!scratch_sig1!!4 signal 01 0
*l0002!scratch_sig1!!3 signal 01 0
*l0002!scratch_sig1!!2 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!dram_sig signal 02 0
.%type R
.%type SI
.%scope global
.%var l0007!temp 0 R
.%liverange 0 B11 95:99
.%liverange 0 ~B11 59:94
.%var $l0006!tmp_data 0 R
.%liverange 0 $W0 90:95
.%liverange 0 $R0 100:100
.%var l0006!tmp_addr 0 R
.%liverange 0 B7 88:99
.%liverange 0 ~B7 59:87
.%var l0005!refcnt 0 R
.%liverange 0 B6 80:99
.%liverange 0 ~B6 59:79
.%var l0005!tbuf_addr 0 R
.%liverange 0 B5 76:77
.%liverange 0 A6 78:99
.%liverange 0 ~A6 59:75
.%var $l0004!tmp_data 0 R
.%liverange 0 $W0 69:89
.%liverange 0 $R0 100:100
.%var l0004!tmp_addr 0 R
.%liverange 0 B10 67:99
.%liverange 0 ~B10 59:66
.%var l0003!mask 0 R
.%liverange 0 B14 60:99
.%liverange 0 ~B14 59:59
.%var $l0003!packet_info 0 R
.%liverange 0 $W0 100:100
.%liverange 0 $R0 61:99
.%liverange 0 ~$R0 59:60
.%var $l0002!scratch_tail 0 R
.%liverange 0 $W2 34:99
.%liverange 0 $R2 100:100
.%var $l0002!scratch_head 0 R
.%liverange 0 $W1 33:58
.%liverange 0 ~$W1 59:96
.%liverange 0 $R1 100:100
.%var $l0002!scratch_base 0 R
.%liverange 0 $W0 35:58
.%liverange 0 ~$W0 59:68
.%liverange 0 $R0 100:100
.%var l0001!temp 0 R
.%liverange 0 B15 4:99
.%var l0000!tbuf 0 R
.%liverange 0 A2 6:99
.%var l0000!dram_addr 0 R
.%liverange 0 B4 64:99
.%liverange 0 ~B4 59:63
.%var l0000!tbuf_mask 0 R
.%liverange 0 B3 7:99
.%var l0000!tbuf_1st_element 0 R
.%liverange 0 B13 10:99
.%var l0000!tbuf_element 0 R
.%liverange 0 B2 73:99
.%liverange 0 ~B2 59:72
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 97:99
.%liverange 0 ~$W1 59:96
.%liverange 0 $R1 100:100
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 96:99
.%liverange 0 ~$W0 59:68
.%liverange 0 $R0 100:100
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W0 16:34
.%liverange 0 $R0 100:100
.%var l0000!txconfigdata0 0 R
.%liverange 0 B9 14:99
.%var l0000!cur_ctx 0 R
.%liverange 0 A1 5:99
.%var l0000!byte_count 0 R
.%liverange 0 A0 62:99
.%liverange 0 ~A0 59:61
.%var l0000!port_count 0 R
.%liverange 0 B1 9:73 75:99
.%liverange 0 A5 74:74
.%var @l0000!packet_count 0 R
.%liverange 0 @B0 0:99
.%var l0000!put_ring_num 0 R
.%liverange 0 B12 12:99
.%var l0000!get_ring_num 0 R
.%liverange 0 A4 11:99
.%var l0000!msfaddress 0 R
.%liverange 0 B8 13:92 94:99
.%liverange 0 A3 93:93
.%var l0006!tmp_scratch_sig 1 R
.%liverange 0 G1 91:91
.%var l0004!tmp_scratch_sig 1 R
.%liverange 0 G1 70:70 72:72
.%var l0003!scratch_sig 1 R
.%liverange 0 G1 61:61
.%var l0002!scratch_sig3 1 R
.%liverange 0 G3 38:39 43:44 48:49 53:54 58:59
.%var l0002!scratch_sig2 1 R
.%liverange 0 G2 37:39 42:44 47:49 52:54 57:59
.%var l0002!scratch_sig1 1 R
.%liverange 0 G1 36:39 41:44 46:49 51:54 56:59
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 100:100
.%var l0000!msf_sig 1 R
.%liverange 0 G1 17:17 21:21 23:23 25:25 27:27 32:32 98:98
.%var l0000!dram_sig 1 R
.%liverange 0 D2 87:92
.%scope end
.0 D800800010 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 57 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.reg l0000!msfaddress l0000!msfaddress0 l0000!msfaddress1
	.%line 58 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.reg l0000!pci_base l0000!get_ring_num l0000!put_ring_num @l0000!packet_count
	.%line 59 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.reg l0000!port_count
	.%line 60 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.reg l0000!byte_count l0000!cur_ctx
	.%line 61 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.reg l0000!txconfigdata0
	.%line 62 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.reg $l0000!txconfigdata0
	.%line 63 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 64 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.reg l0000!tbuf_element l0000!tbuf_1st_element l0000!tbuf_mask
	.%line 65 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.reg l0000!dram_addr l0000!tbuf
	.%line 66 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.sig l0000!dram_sig l0000!msf_sig l0000!interthd_sig
	.%line 68 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.xfer_order $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 70 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.addr l0000!interthd_sig 15
	.%line 71 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
	.set_sig l0000!interthd_sig
	.%line 73 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0 2
	init_value#:
	.%line 74 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0 2
		br=ctx[0, init_all#]
.1 E000010000 common_code
	.%line 75 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		ctx_arb[kill], any
.2 FC044C0000 common_code
	.%line 78 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		.local l0001!temp
	.%line 77 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 1
	init_all#:
	.%line 79 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 1
		local_csr_rd[active_ctx_sts]
.3 F000003F00 common_code
	.%line 80 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 0
		immed[l0001!temp, 0]
.4 A400103F07 common_code
	.%line 81 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		alu[l0000!cur_ctx, 0x7, and, l0001!temp]
.5 F0020C0002 common_code
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		.endlocal
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		immed[l0000!tbuf, 0x2000]
.6 F000000F3F common_code
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		immed[l0000!tbuf_mask, 63]
.7 F000020300 common_code
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		immed[@l0000!packet_count, 0]
.8 F000000700 common_code
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		immed[l0000!port_count, 0]
.9 91C0D80201 common_code
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		alu_shf[l0000!tbuf_1st_element, --, b, l0000!cur_ctx, <<4]
.10 81E0480201 common_code
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		alu_shf[l0000!get_ring_num , --, b, l0000!cur_ctx, <<2]
.11 91E0C09200 common_code
	.%line 91 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		alu_shf[l0000!put_ring_num , --, b, 4, <<2]
.12 F000002304 common_code
	.%line 97 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		immed[l0000!msfaddress, 0x0004]
.13 F000002704 common_code
	.%line 98 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		immed[l0000!txconfigdata0, 4]
.14 F440102700 common_code
	.%line 99 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		immed_w1[l0000!txconfigdata0, 256]
.15 A018002400 common_code
	.%line 100 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		alu[$l0000!txconfigdata0, --, b, l0000!txconfigdata0]
.16 3D10002020 common_code
	.%line 101 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		msf[write, $l0000!txconfigdata0, 0, l0000!msfaddress, 1], ctx_swap[l0000!msf_sig]
.17 F00000271D common_code
	.%line 108 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		immed[l0000!txconfigdata0, 29]
.18 A018002400 common_code
	.%line 109 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		alu[$l0000!txconfigdata0, --, b, l0000!txconfigdata0]
.19 F000002390 common_code
	.%line 110 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		immed[l0000!msfaddress, 0x0090]
.20 3D10002020 common_code
	.%line 111 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0
		msf[write, $l0000!txconfigdata0, 0, l0000!msfaddress, 1], ctx_swap[l0000!msf_sig]
.21 F000002394 common_code
	.%line 112 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_tx.uc" 1 0