dual_bd_in_rx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.6.354
+uca_date: Jan 20 2004 14:03:45
+current_date: Tue Mar 02 11:59:07 2004

.cpu_version 0x00000002 16 255

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

.%legacy xfer on

:cont_init1# 3
:cont_init2# 21
:init_rbuf# 28
:init_value# 2
:receivepacket# 48
:rsw# 50
:set_refcnt_overwrite_bit# 58
*-- no_destination 0
*$l0000!transferreg00 sram_rel 00 0 both 2 0x34
*$l0000!transferreg01 sram_rel 01 0 both 1 0x34
;*l0000!rxthreadlist!!2 gpr_b_rel 05
;*l0000!rxthreadlist!!3 gpr_b_rel 05
*l0000!rxthreadlist gpr_a_rel 07
*l0000!bytecnt gpr_b_rel 04
*l0000!elem gpr_a_rel 00
*l0000!error gpr_b_rel 05
*l0000!rx_channel_num gpr_b_rel 06
*l0000!cur_ctx gpr_a_rel 06
*@l0000!packet_count gpr_b_abs 00
;*l0000!rxconfigdata!!2 gpr_a_rel 01
*l0000!rxconfigdata gpr_b_rel 06
*l0000!rbuf gpr_a_rel 02
*l0000!ring_num gpr_b_rel 03
;*l0000!msfaddress!!2 gpr_b_rel 0C
;*l0000!msfaddress!!3 gpr_b_rel 0C
;*l0000!msfaddress!!4 gpr_b_rel 0C
;*l0000!msfaddress!!5 gpr_b_rel 0C
;*l0000!msfaddress!!6 gpr_b_rel 0C
*l0000!msfaddress gpr_b_rel 0C
*l0000!threadfreelist_addr gpr_b_rel 01
*l0000!elementdone_addr gpr_a_rel 03
;*l0000!drampacketbase!!2 gpr_b_rel 02
*l0000!drampacketbase gpr_b_rel 02
*l0000!put_ring_num gpr_b_rel 03
*l0000!rx_count_ring_num gpr_a_rel 04
*l0001!temp gpr_b_rel 04
*l0001!cur_me gpr_b_rel 02
*l0002!rxconfigdata0 gpr_b_rel 0D
*$l0002!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0003!temp_reg gpr_b_rel 07
*l0003!temp gpr_b_rel 08
*l0004!rxupcontrol gpr_b_rel 0E
*$l0004!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0005!rxconfigdata0 gpr_b_rel 0F
*$l0005!rxconfigdata0 sram_rel 00 0 both 1 0x0
*l0006!rbufoffset gpr_b_rel 09
;*l0006!refcnt!!2 gpr_a_rel 05
*l0006!refcnt gpr_b_rel 0A
;*l0006!temp!!2 gpr_b_rel 0B
;*l0006!temp!!3 gpr_b_rel 0B
*l0006!temp gpr_b_rel 0B
*$l0007!temp0 sram_rel 00 0 both 1 0x0
*$l0008!scratch_data sram_rel 00 0 both 1 0x0
*$l0008!scratch_packet_count sram_rel 01 0 both 1 0x0
*l0008!scratch_sig2 signal 02 0
*l0008!scratch_sig1 signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!rx_sig_thd signal 02 0
*l0000!sig_dram_xfer1 signal 02 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!7 signal 01 0
*l0000!msf_sig!!6 signal 01 0
*l0000!msf_sig!!5 signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
.%type R
.%type SI
.%scope global
.%var $l0008!scratch_packet_count 0 R
.%liverange 0 $W1 70:73
.%liverange 0 ~$W1 48:69
.%liverange 0 $R1 74:74
.%var $l0008!scratch_data 0 R
.%liverange 0 $W0 69:73
.%liverange 0 ~$W0 48:65
.%liverange 0 $R0 74:74
.%var $l0007!temp0 0 R
.%liverange 0 $W0 66:68
.%liverange 0 $R0 74:74
.%var l0006!temp 0 R
.%liverange 0 B11 61:73
.%liverange 0 ~B11 48:60
.%var l0006!refcnt 0 R
.%liverange 0 B10 55:58
.%liverange 0 A5 59:73
.%liverange 0 ~A5 48:54
.%var l0006!rbufoffset 0 R
.%liverange 0 B9 60:73
.%liverange 0 ~B9 48:59
.%var $l0005!rxconfigdata0 0 R
.%liverange 0 $W0 46:47
.%liverange 0 ~$W0 48:65
.%liverange 0 $R0 74:74
.%var l0005!rxconfigdata0 0 R
.%liverange 0 B15 44:73
.%var $l0004!rxconfigdata0 0 R
.%liverange 0 $W0 35:45
.%liverange 0 $R0 74:74
.%var l0004!rxupcontrol 0 R
.%liverange 0 B14 34:73
.%var l0003!temp 0 R
.%liverange 0 B8 29:73
.%liverange 0 ~B8 28:28
.%var l0003!temp_reg 0 R
.%liverange 0 B7 28:73
.%var $l0002!rxconfigdata0 0 R
.%liverange 0 $W0 25:34
.%liverange 0 $R0 74:74
.%var l0002!rxconfigdata0 0 R
.%liverange 0 B13 23:73
.%var l0001!cur_me 0 R
.%liverange 0 B2 6:13
.%var l0001!temp 0 R
.%liverange 0 B4 5:47
.%liverange 0 ~B4 48:51
.%var l0000!rx_count_ring_num 0 R
.%liverange 0 A4 18:73
.%var l0000!put_ring_num 0 R
.%liverange 0 B3 17:73
.%var l0000!drampacketbase 0 R
.%liverange 0 B2 14:73
.%var l0000!elementdone_addr 0 R
.%liverange 0 A3 19:73
.%var l0000!threadfreelist_addr 0 R
.%liverange 0 B1 3:73
.%var l0000!msfaddress 0 R
.%liverange 0 B12 26:73
.%var l0000!ring_num 0 R
.%liverange 0 B3 8:16
.%var l0000!rbuf 0 R
.%liverange 0 A2 20:73
.%var l0000!rxconfigdata 0 R
.%liverange 0 B6 12:12
.%liverange 0 A1 13:73
.%var @l0000!packet_count 0 R
.%liverange 0 @B0 0:73
.%var l0000!cur_ctx 0 R
.%liverange 0 A6 7:73
.%var l0000!rx_channel_num 0 R
.%liverange 0 B6 54:73
.%liverange 0 ~B6 48:53
.%var l0000!error 0 R
.%liverange 0 B5 53:73
.%liverange 0 ~B5 48:52
.%var l0000!elem 0 R
.%liverange 0 A0 51:73
.%liverange 0 ~A0 48:50
.%var l0000!bytecnt 0 R
.%liverange 0 B4 52:73
.%liverange 0 ~B4 48:51
.%var l0000!rxthreadlist 0 R
.%liverange 0 A7 9:9
.%liverange 0 B5 10:47
.%liverange 0 ~B5 48:52
.%var $l0000!transferreg01 0 R
.%liverange 0 $W1 74:74
.%liverange 0 $R1 74:74
.%var $l0000!transferreg00 0 R
.%liverange 0 $W0 0:24
.%liverange 0 $R0 0:73
.%var l0008!scratch_sig2 1 R
.%liverange 0 G2 72:73
.%var l0008!scratch_sig1 1 R
.%liverange 0 G1 71:73
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 74:74
.%var l0000!rx_sig_thd 1 R
.%liverange 0 G2 48:50
.%var l0000!sig_dram_xfer1 1 R
.%liverange 0 D2 64:65
.%var l0000!msf_sig 1 R
.%liverange 0 G1 27:27 37:37 39:39 41:41 43:43 48:48 67:67
.%scope end
.0 D800800010 common_code
	.import_var __chip_id i$__chip_id __chip_revision i$__chip_revision __uengine_id i$__uengine_id
	.%line 60 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.reg $l0000!transferreg00 $l0000!transferreg01
	.%line 61 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.reg l0000!rxthreadlist l0000!bytecnt l0000!elem l0000!error l0000!rx_channel_num
	.%line 62 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.reg l0000!cur_ctx
	.%line 63 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.reg @l0000!packet_count
	.%line 64 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.reg l0000!rxconfigdata
	.%line 65 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.reg l0000!rbuf l0000!ring_num
	.%line 66 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.reg l0000!msfaddress l0000!threadfreelist_addr l0000!elementdone_addr
	.%line 67 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.reg l0000!drampacketbase
	.%line 68 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.reg l0000!put_ring_num l0000!rx_count_ring_num
	.%line 69 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.sig l0000!msf_sig l0000!sig_dram_xfer1
	.%line 70 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.sig l0000!rx_sig_thd l0000!interthd_sig
	.%line 71 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.xfer_order $l0000!transferreg00 $l0000!transferreg01
	.%line 73 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.addr l0000!interthd_sig 15
	.%line 75 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.set $l0000!transferreg00
	.%line 76 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.set_sig l0000!interthd_sig
	.%line 78 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0 2
		br=ctx[0, init_value#]
.1 E000010000 common_code
	.%line 79 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
		ctx_arb[kill], any
.2 F000000730 common_code
	.%line 81 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	init_value#:
	.%line 82 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
		immed[l0000!threadfreelist_addr, 0x0030]
.3 FC044C0000 common_code
	.%line 85 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
	.begin
	.%line 86 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
		.reg l0001!temp l0001!cur_me
	.%line 84 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 1
	cont_init1#:
	.%line 87 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 1
		local_csr_rd[active_ctx_sts]
.4 F000001300 common_code
	.%line 88 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 0
		immed[l0001!temp, 0]
.5 943020112F common_code
	.%line 89 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
		alu_shf[l0001!cur_me, 0xf, and, l0001!temp, >>3]
.6 A400601307 common_code
	.%line 90 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
		alu[l0000!cur_ctx, 0x7, and, l0001!temp]
.7 91E0380206 common_code
	.%line 91 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
		alu_shf[l0000!ring_num, --, b, l0000!cur_ctx, <<2]
.8 F0020C0007 common_code
	.%line 93 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
		immed[l0000!rxthreadlist, 8192]
.9 9B90500A07 common_code
	.%line 94 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
		alu_shf[l0000!rxthreadlist, l0000!rxthreadlist, or, l0001!cur_me, <<7]
.10 9BC0581606 common_code
	.%line 95 "C:\phase9rel\diag\test_suites\microcode\dual_bd_loopback\dual_bd_rx.uc" 1 0
		alu_shf[l0000!rxthreadlist, l0000!rxthreadlist, or, l0000!cur_ctx, <<4]