line_rate_bd_eg_tx.list

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

+version:  10/31/2000
+switches:  
+uca_version: 3.0.411
+uca_date: Sep  9 2002 00:25:20
+current_date: Mon Dec 02 18:51:07 2002

.cpu_version 0x00000002 0 15

.%num_contexts 8

.%local_mem0_mode rel
.%local_mem1_mode rel

.%init_nn_mode neighbor

:cont1# 58
:init# 5
:init_common# 0
:transmit# 49
:wait_for_assignment# 39
:wait_for_next_ctx_sig# 38
*-- no_destination 0
;*l0000!temp!!2 gpr_b_rel 04
;*l0000!temp!!3 gpr_a_rel 06
;*l0000!temp!!4 gpr_a_rel 06
*l0000!temp gpr_b_rel 04
;*l0000!msfaddress!!2 gpr_b_rel 05
;*l0000!msfaddress!!3 gpr_b_rel 05
*l0000!msfaddress gpr_b_rel 05
*l0000!byte_count gpr_a_rel 00
*l0000!ring_num gpr_b_rel 00
*l0000!mask_qa gpr_b_rel 01
;*l0000!txconfigdata0!!2 gpr_a_rel 07
;*l0000!txconfigdata0!!3 gpr_a_rel 07
*l0000!txconfigdata0 gpr_a_rel 07
*$l0000!txconfigdata0 sram_rel 00 0 both 1 0x0
*$l0000!txcontrolword0 sram_rel 00 0 both 2 0x21
*$l0000!txcontrolword1 sram_rel 01 0 both 1 0x21
*$l0000!scratch_data0 sram_rel 00 0 both 2 0x1D
*$l0000!scratch_data1 sram_rel 01 0 both 1 0x1D
*@l0000!tbuf_element gpr_b_abs 02
*l0000!cur_tbuf_elem gpr_a_rel 01
*l0000!buf_addr gpr_a_rel 02
*l0000!tbuf gpr_b_rel 03
;*l0000!cur_tbuf_addr!!2 gpr_b_rel 06
;*l0000!cur_tbuf_addr!!3 gpr_a_rel 03
*l0000!cur_tbuf_addr gpr_b_rel 06
*@l0000!sramdescbase gpr_b_abs 12
*@l0000!drampacketbase gpr_b_abs 22
*@l0000!t0 gpr_b_abs 32
;*l0001!channel_number!!2 gpr_b_rel 07
*l0001!channel_number gpr_b_rel 07
*$l0002!scratch_base sram_rel 00 0 both 1 0x0
*$l0002!scratch_head sram_rel 01 0 both 1 0x0
*$l0002!scratch_tail sram_rel 02 0 both 1 0x0
;*l0003!refcnt!!2 gpr_b_rel 08
;*l0003!refcnt!!3 gpr_b_rel 08
*l0003!refcnt gpr_b_rel 08
;*l0003!pkt_buf_addr!!2 gpr_a_rel 04
*l0003!pkt_buf_addr gpr_a_rel 04
;*l0004!msfaddress!!2 gpr_a_rel 05
*l0004!msfaddress gpr_b_rel 09
*l0005!cellcount gpr_a_rel 08
*l0005!t0 gpr_b_rel 0A
*l0002!scratch_sig3 signal 03 0
*l0002!scratch_sig2 signal 02 0
*l0002!scratch_sig1 signal 01 0
*l0000!next_ctx_sig signal 04 0
*l0000!scratch_sig signal 01 0
*l0000!interthd_sig signal 0F 0
*l0000!msf_sig signal 01 0
*l0000!msf_sig!!4 signal 01 0
*l0000!msf_sig!!3 signal 01 0
*l0000!msf_sig!!2 signal 01 0
*l0000!dram_sig signal 02 0
.%type R
.%type SI
.%scope global
.%var l0005!t0 0 R
.%liverange 0 B10 73:78
.%liverange 0 ~B10 39:72
.%var l0005!cellcount 0 R
.%liverange 0 A8 76:78
.%liverange 0 ~A8 39:75
.%var l0004!msfaddress 0 R
.%liverange 0 B9 65:65
.%liverange 0 A5 66:78
.%liverange 0 ~A5 39:64
.%var l0003!pkt_buf_addr 0 R
.%liverange 0 A4 50:78
.%liverange 0 ~A4 39:49
.%var l0003!refcnt 0 R
.%liverange 0 B8 55:78
.%liverange 0 ~B8 39:54
.%var $l0002!scratch_tail 0 R
.%liverange 0 $W2 16:37
.%liverange 0 ~$W2 39:78
.%liverange 0 $R2 79:79
.%var $l0002!scratch_head 0 R
.%liverange 0 $W1 15:37
.%liverange 0 ~$W1 39:68
.%liverange 0 $R1 79:79
.%var $l0002!scratch_base 0 R
.%liverange 0 $W0 14:23
.%liverange 0 $R0 79:79
.%var l0001!channel_number 0 R
.%liverange 0 B7 11:37
.%liverange 0 ~B7 39:78
.%var @l0000!t0 0 R
.%liverange 0 @B50 0:78
.%var @l0000!drampacketbase 0 R
.%liverange 0 @B34 0:78
.%var @l0000!sramdescbase 0 R
.%liverange 0 @B18 0:78
.%var l0000!cur_tbuf_addr 0 R
.%liverange 0 B6 52:53
.%liverange 0 A3 54:78
.%liverange 0 ~A3 39:51
.%var l0000!tbuf 0 R
.%liverange 0 B3 4:78
.%var l0000!buf_addr 0 R
.%liverange 0 A2 43:78
.%liverange 0 ~A2 39:42
.%var l0000!cur_tbuf_elem 0 R
.%liverange 0 A1 45:78
.%liverange 0 ~A1 39:44
.%var @l0000!tbuf_element 0 R
.%liverange 0 @B2 0:78
.%var $l0000!scratch_data1 0 R
.%liverange 0 $W1 79:79
.%liverange 0 $R1 79:79
.%var $l0000!scratch_data0 0 R
.%liverange 0 $W0 79:79
.%liverange 0 $R0 40:78
.%liverange 0 ~$R0 39:39
.%var $l0000!txcontrolword1 0 R
.%liverange 0 $W1 69:78
.%liverange 0 ~$W1 39:68
.%liverange 0 $R1 79:79
.%var $l0000!txcontrolword0 0 R
.%liverange 0 $W0 68:78
.%liverange 0 ~$W0 39:67
.%liverange 0 $R0 79:79
.%var $l0000!txconfigdata0 0 R
.%liverange 0 $W0 24:37
.%liverange 0 ~$W0 39:67
.%liverange 0 $R0 79:79
.%var l0000!txconfigdata0 0 R
.%liverange 0 A7 22:37
.%liverange 0 ~A7 39:78
.%var l0000!mask_qa 0 R
.%liverange 0 B1 1:78
.%var l0000!ring_num 0 R
.%liverange 0 B0 3:78
.%var l0000!byte_count 0 R
.%liverange 0 A0 44:78
.%liverange 0 ~A0 39:43
.%var l0000!msfaddress 0 R
.%liverange 0 B5 21:37
.%liverange 0 ~B5 39:78
.%var l0000!temp 0 R
.%liverange 0 B4 35:37 67:73
.%liverange 0 ~B4 39:66
.%liverange 0 A6 74:78
.%liverange 0 ~A6 39:66
.%var l0002!scratch_sig3 1 R
.%liverange 0 G3 19:20
.%var l0002!scratch_sig2 1 R
.%liverange 0 G2 18:20
.%var l0002!scratch_sig1 1 R
.%liverange 0 G1 17:20
.%var l0000!next_ctx_sig 1 R
.%liverange 0 G4 38:39 64:71
.%var l0000!scratch_sig 1 R
.%liverange 0 G1 40:40
.%var l0000!interthd_sig 1 R
.%liverange 0 G15 79:79
.%var l0000!msf_sig 1 R
.%liverange 0 G1 25:25 29:29 34:34 70:71
.%var l0000!dram_sig 1 R
.%liverange 0 D2 63:64
.%scope end
.0 F00FF007FF common_code
	.import_var __chip_id __chip_revision __uengine_id
	.%line 71 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg l0000!sram_addr
	.%line 72 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg l0000!temp $l0000!temp
	.%line 73 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg l0000!msfaddress l0000!msfaddress0 l0000!msfaddress1
	.%line 74 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg l0000!byte_count l0000!ring_num l0000!mask_qa
	.%line 75 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg l0000!pci_base l0000!mailbox0 l0000!mailbox1 $l0000!pci_rw0 $l0000!pci_rw1
	.%line 76 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg l0000!txconfigdata0
	.%line 77 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg $l0000!txconfigdata0
	.%line 78 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 79 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg $l0000!scratch_data0 $l0000!scratch_data1
	.%line 80 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg @l0000!tbuf_element l0000!cur_tbuf_elem
	.%line 81 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg l0000!buf_addr l0000!pkt_buff_addr l0000!tbuf l0000!cur_tbuf_addr
	.%line 82 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.reg @l0000!sramdescbase @l0000!drampacketbase @l0000!t0 @l0000!wait
	.%line 83 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.sig l0000!dram_sig l0000!msf_sig l0000!interthd_sig l0000!cap_sig l0000!scratch_sig l0000!next_ctx_sig
	.%line 84 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.sig l0000!pci_sig0 l0000!pci_sig1
	.%line 85 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.sig l0000!sram_sig
	.%line 87 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.xfer_order $l0000!txcontrolword0 $l0000!txcontrolword1
	.%line 88 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.xfer_order $l0000!scratch_data0 $l0000!scratch_data1
	.%line 90 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.addr l0000!interthd_sig 15
	.%line 91 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.set_sig l0000!interthd_sig l0000!next_ctx_sig
	.%line 93 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	init_common#:
	.%line 94 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		immed[l0000!mask_qa, 65535]
.1 F4400007FF common_code
	.%line 95 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		immed_w1[l0000!mask_qa, 255]
.2 F000000300 common_code
	.%line 96 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		immed[l0000!ring_num, 0]
.3 F002000F00 common_code
	.%line 97 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		immed[l0000!tbuf, 0x2000]
.4 D809800011 common_code
	.%line 99 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0 38
		br!=ctx[0, wait_for_next_ctx_sig#]
.5 F000020B00 common_code
	.%line 101 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	init#:
	.%line 102 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		immed[@l0000!tbuf_element, 0]
.6 F000024B00 common_code
	.%line 104 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		immed[@l0000!sramdescbase, 0]
.7 F440024B20 common_code
	.%line 105 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		immed_w1[@l0000!sramdescbase, 32]
.8 F000028B00 common_code
	.%line 107 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		immed[@l0000!drampacketbase, 0]
.9 F440128B00 common_code
	.%line 108 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		immed_w1[@l0000!drampacketbase, 256]
.10 9020708600 common_code
	.%line 110 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
	.begin
	.%line 111 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		.reg l0001!channel_number
	.%line 112 "C:\Angel-Island\diag\test_suites\microcode\line_rate_bd\line_rate_bd_eg_tx.uc" 1 0
		alu_shf[l0001!channel_number, --, b, 1, <<30]