📄 line_rate_bd_eg_rx.uc
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/* line_rate_eg_rx.uc
*
* This line rate test is not a performance benchmark. It will be used to
* verify whether the system is able to handle the data traffic that is
* pumped to the media port at whatever line rate that is pumped into the
* system. A packet generator will be required for this test.
*
* NOTE: THIS IS NOT A PERFORMANCE BENCHMARK!!!! IT IS JUST TO CHECK IF THE
* HARDWARE IS ABLE TO HANDLE DATA AT THE LINERATE THAT IS BEING
* PUMPED INTO THE SYSTEM
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, April, 2002
* revisions: dalsraja, May 8, 2002
*
*
* --------------------------------------------------------------------------
*/
#include "common_uc.h"
#define RX_SINGLE_PHY MSF_SINGLE_PHY
#define RX_WIDTH MSF_WIDTH_1x32
#define RX_ENABLE_MASK 0x1
#define RX_MODE MSF_CSIX
#define RX_ELEMENT_SIZE MSF_ELEMENTSIZE_128
#define RBUF_ELEM_COUNT (((1 << (7 - RX_ELEMENT_SIZE)) >> 2) * 3) // (Tot. elements / 4) * 3
#define RX_ELEMENTSIZE_BYTE (1 << (6 + RX_ELEMENT_SIZE))
#define RX_TRANSFER_THREAD &$TransferReg00
#define RX_SIGNAL_THREAD &rx_sig_thd
#define NEXT_CTX_SIGNAL &next_ctx_sig
#define SIG_CTX (0x80 | NEXT_CTX_SIGNAL << 3)
#define SRAM_DESC_BASE 0x200000 // 2 Meg onwards
#define DRAM_PCKT_BASE 0x1000000 // 16 Meg onwards
#define CELL_COUNT 1
#define FULL 0xFFFFFFFF
#define ME_NUMBER_RX 0
#define ME_NUMBER_TX 1
#define RX_THD_NUM 0
#define TX_THD_NUM 0
#define INTER_ME_SIG_NUM 15
#define SIG_INIT_DONE_TO_XSCALE_ADDR 0x4000
#define PATTERN_INIT_DONE_TO_XSCALE 0xCACACACA
#define BUFFER_ADDR_MASK 0xFFFFFF
.reg $TransferReg00 $TransferReg01
.reg $scratch_base $scratch_head $scratch_tail channel_number t0
.reg $temp0 $temp1 temp
.reg RxThreadList MsfAddress sopbit eopbit bytecnt elem
.reg class seq_num pkt_len channelNum
.reg RxConfigData $RxConfigData0 RxConfigData0 null error
.reg rbuf Rbufoffset ring bdptr
.reg L2Port MsfAddress0 MsfAddress1
.reg @sramDescBase @dramPacketBase
.reg pkt_buff_addr mask_qa dram_refcnt
.reg $sr0 $sr1 $sr2 $sr3 got_pkt @counter
.reg pci_base mailbox0 mailbox1 mailbox2 mailbox3 $pci_rw0 $pci_rw1 @wait
.sig MSF_SIG MSF_SIG1 MSF_SIG2 scratch_sig sig_dram_xfer1
.sig sig_free_buf rx_sig_thd pci_sig0 pci_sig1
.sig qa_init next_ctx_sig
.sig interthd_sig
.xfer_order $sr0 $sr1 $sr2 $sr3
.set $TransferReg00 $TransferReg01
.set_sig next_ctx_sig
.addr interthd_sig INTER_ME_SIG_NUM
.set_sig interthd_sig
here#:
immed[got_pkt, 0]
immed[mask_qa, (BUFFER_ADDR_MASK & MASK_16BIT)]
immed_w1[mask_qa, ((BUFFER_ADDR_MASK >> 16) & MASK_16BIT)] // Used to mask out the buffer address on dequeue
alu[channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
alu[t0, channel_number, OR, Q_NUMBER, <<SRAM_Q_ARRAY_NUMBER_FIELD]
br!=ctx[0, InitStart#], defer[1]
alu_shf[ring, --, b, RING_0, <<2] // ring number in a register
Init_Value#:
immed[@counter, 0]
immed[@sramDescBase, (SRAM_DESC_BASE & MASK_16BIT)]
immed_w1[@sramDescBase, ((SRAM_DESC_BASE >> 16) & MASK_16BIT)]
immed[@dramPacketBase, (DRAM_PCKT_BASE & MASK_16BIT)]
immed_w1[@dramPacketBase, ((DRAM_PCKT_BASE >> 16) & MASK_16BIT)]
ctx_arb[interthd_sig]
context_enable_csr_config#:
//**********************************************************
// Program CSR Context Enables, used by the context arbiter
//**********************************************************
// Initialize CTX_Enables CSR (Put into 8 CTX mode)
// Bit 31: In-Use contexts: 0 = 8 ctx mode, 1 = 4 ctx mode
// Bit 20: Next Neigher registers are written from this ME
// Bit 17, 1=LM_ADDR_1 is GLOBAL, 0=LM_ADDR_1 is context_relative
// Bit 16, 1=LM_ADDR_0 is GLOBAL, 0=LM_ADDR_0 is context_relative
// Bits [15:8] CTX enables for contexts 7:0
#define In_Use_Contexts 0
#define Control_Store_Parity_Error 0
#define Control_Store_Parity_Enable 0
#define Breakpoint 0
#define NN_Mode 1
#define NN_Ring_Empty 0
#define LM_ADDR_1_Global 0
#define LM_ADDR_0_Global 0
#define Enable 0xff
//****************************************************
// Configure RX/TX Control
//****************************************************
immed[RxConfigData0, ((0<<9) | (RX_ELEMENT_SIZE << 2))] // put control and data into diff freelist
immed_w1[RxConfigData0, ((RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
alu[$RxConfigData0, --, B, RxConfigData0]
immed[MsfAddress, MSF_RX_CONTROL]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[MSF_SIG1]
alu[$temp1, --, B, MSF_CSIX_RBUF_DATA, <<BIT_SHF_UNICAST]
immed[MsfAddress, CSIX_TYPE_MAP]
msf[write, $temp1, MsfAddress, 0, 1], ctx_swap[MSF_SIG1]
//*****************************************
// Init q descriptor. Q format head/tail ptr=0,
//******************************************
.begin
.reg sw0 sw1 sw2 sw3 cellcount freelist sr0
.reg $s0 $s1 $s2
.reg tmp spin
.sig qa_init addr
.xfer_order $s0 $s1 $s2
alu[tmp, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
alu[tmp, tmp, OR, @sramDescBase]
immed[$s0, 0]
immed[$s1, 0]
immed[$s2, 0]
sram[write, $s0, tmp, 0, 3], ctx_swap[qa_init]
alu[tmp, --, B, @sramDescBase]
alu[tmp, --, B, tmp, >>2]
sram[rd_qdesc_head, $sr0, t0, tmp, 2], ctx_swap[qa_init]
sram[rd_qdesc_other, --, t0, tmp]
immed[freelist, (FREELIST_SIZE & MASK_16BIT)]
immed_w1[freelist, ((FREELIST_SIZE >> 16) & MASK_16BIT)]
immed[cellcount, 0x1c, <<16] //set cell count to 1, set OV EOP, and SOP
addfreelist#:
alu[--, cellcount, OR, 0]
sram[enqueue, --, t0, tmp], indirect_ref
alu[tmp, tmp, +, 1]
alu[freelist, freelist, -, 1]
bne[addfreelist#]
.end
//******************************************************
// Initialize RBUF Freelist to add elements to the list
//******************************************************
.begin
.reg temp_reg
immed[temp_reg, 0]
init_RBUF#:
alu[temp, --, B, temp_reg, <<16]
msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
alu[temp_reg, temp_reg, +, 1]
alu[--, RBUF_ELEM_COUNT, -, temp_reg]
bne[init_RBUF#]
.end
immed[RxConfigData0, ((0 << 9) | (RX_ELEMENT_SIZE << 2))] // put control and data into diff freelist
immed_w1[RxConfigData0, ((RX_ENABLE_MASK << 12) | (RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
alu[$RxConfigData0, --, B, RxConfigData0]
immed[MsfAddress, MSF_RX_CONTROL]
msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[MSF_SIG1]
//******************************************************
// Configure Rx_Thread_Freelist_Timeout0
//******************************************************
immed[temp, FREELIST_TIMEOUT_VAL]
alu[temp,--, B, temp, <<16] // timeout value in ms16 bits
msf[fast_wr, --, temp, RX_THREAD_FREELIST_TIMEOUT_0]
//*******************************************
// Configure Ctx_Enables
//*******************************************
.begin
.reg CtxEnableData
immed[CtxEnableData, (Enable << 8)]
immed_w1[CtxEnableData, ((In_Use_Contexts << 15)|(Control_Store_Parity_Error << 13)|(Control_Store_Parity_Enable << 12)|(Breakpoint << 11)|(NN_Mode << 4)|(NN_Ring_Empty << 2)|(LM_ADDR_1_Global << 1)|(LM_ADDR_0_Global << 0))]
local_csr_wr[CTX_Enables, CtxEnableData]
.end
//********************************************************
// Start of Test
//********************************************************
start#:
.xfer_order $TransferReg00 $TransferReg01
.xfer_order $temp0 $temp1
//*******************************************************
// Configure RX Thread List CSRs
// add thread id to free list and wait on signal
//*******************************************************
InitStart#:
.begin
.reg cur_me, cur_ctx
local_csr_rd[ACTIVE_CTX_STS]
immed[temp, 0]
alu[cur_me, 0xF, AND, temp, >>3] // Extract the current ME number
alu[cur_ctx, 0x7, AND, temp] // Extract the current context number
immed[RxThreadList, (RX_SIGNAL_THREAD << 12)]
alu[RxThreadList, RxThreadList, OR, cur_me, <<7]
alu[RxThreadList, RxThreadList, OR, cur_ctx, <<4]
.end
Init_Common#:
.set_sig next_ctx_sig
immed[rbuf, RBUF_TBUF ]
immed[MsfAddress0, RX_THREAD_FREELIST_0]
immed[MsfAddress1, RBUF_ELEMENT_DONE]
alu[RxConfigData, RxThreadList, OR , RX_TRANSFER_THREAD]
alu[RxConfigData, --, B, RxConfigData, <<16] // For msf[fast_wr...]
br=ctx[0, ReceivePacket#] // If ctx 0, branch to label
ctx_arb[next_ctx_sig]
ReceivePacket#:
.set_sig rx_sig_thd next_ctx_sig
local_csr_wr[SAME_ME_SIGNAL, SIG_CTX]
msf[fast_wr, --, MsfAddress0, RxConfigData] // add thread to freelist
ctx_arb[rx_sig_thd, next_ctx_sig]
// RSW should be in xfer register
// Transfer RBUF data to sram_in transfer registers
//***************************************
// Extract RSW
//***************************************
RSW#:
alu[null, 0x1, AND, $TransferReg00, >>9] // Extract null
bne[NULL#] // If null=1, result=0
.set_sig next_ctx_sig
local_csr_wr[SAME_ME_SIGNAL, SIG_CTX]
alu_shf[elem, 0xFF, AND, $TransferReg00, >>24] // get element number
alu_shf[bytecnt, 0xFF, AND, $TransferReg00, >>16] // get pkt len
alu_shf[error, 0x1, AND, $TransferReg00, >>13]
//*******************************
// Check error bit
//*******************************
/* alu[--, error, AND, 1]
bne[increment_rx_error_counter#]
*/
SOP_EOP#:
sram[dequeue, $sr0, t0, 0], sig_done[sig_free_buf]
ctx_arb[sig_free_buf, next_ctx_sig]
//*********************************
// Transfer from ME to DRAM
//*********************************
.begin
.reg pkt_buff_addr rel RBufOffset refcnt freebuffer
.set_sig next_ctx_sig
local_csr_wr[SAME_ME_SIGNAL, SIG_CTX]
alu[freebuffer, --, B, $sr0, <<2] // Shift 2 as address obtained is longword address
alu[rel, freebuffer, -, @sramDescBase]
alu[rel, --, B, rel, <<5]
alu[pkt_buff_addr, @dramPacketBase, +, rel]
alu[refcnt, --, B, bytecnt, >>3]
alu[--, bytecnt, AND, 0x7]
bne[cont1#]
alu[refcnt, refcnt, -, 1]
cont1#:
alu[refcnt, refcnt, OR, 1, <<4] // Set the overwrite bit for refcnt
alu[RBufOffset, --, B, elem, <<7] // 128B
alu[temp, RBuf, +, RBufOffset]
alu[temp, 16, OR, temp, <<5] // shift rbuf addr and set the overwrite bit
alu[temp, temp, OR, refcnt, <<21] // shift refcnt and add for indirect ref
dram[rbuf_rd, --, pkt_buff_addr, 0, 8], indirect_ref, sig_done[sig_dram_xfer1]
scratch_write#:
alu[bdptr, freebuffer, -, @sramDescBase]
alu[$temp0, bdptr, OR, bytecnt, <<24]
fill#:
br_inp_state[SCR_Ring0_Full, fill#]
scratch[put, $temp0, ring, 0, 1], sig_done[scratch_sig]
ctx_arb[sig_dram_xfer1, scratch_sig, next_ctx_sig]
.end
//**************************************************************
// Free up Element by writing to RBUF_Element_Done{Channel} 3
//**************************************************************
alu[temp, --, B, elem, <<16]
msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
// loop around and wait for next packet
NULL#:
br[ReceivePacket#]⌨️ 快捷键说明
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