rbuf_flush_6048_1port.uc

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* workaround_6048.uc
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXDP2400
 *  subsystem: DIAG
 *  author: dalsraja, April, 2002
 *  revisions: dalsraja, May 8, 2002
 * 
 * 
 * --------------------------------------------------------------------------
 */

#include "common_uc.h"

#define RX_SINGLE_PHY					MSF_SINGLE_PHY
#define RX_WIDTH						MSF_WIDTH_1x32
#define RX_ENABLE_MASK					0x1
#define RX_MODE							MSF_POS_UTOPIA
#define RX_ELEMENTSIZE					MSF_ELEMENTSIZE_128
#define RBUF_ELEM_COUNT					(1 << (7 - RX_ELEMENTSIZE))
#define RX_ELEMENTSIZE_BYTE				(1 << (6 + RX_ELEMENTSIZE))

#define RX_TRANSFER_THREAD				&$TransferReg00
#define RX_SIGNAL_THREAD				&rx_sig_thd

#define SRAM_DESC_BASE					0x200000		// 2 Meg onwards
#define DRAM_PCKT_BASE					0x1000000		// 16 Meg onwards

#define CELL_COUNT						1

#define FULL							0xFFFFFFFF

#define ME_NUMBER_Rx					0
#define ME_NUMBER_Tx					1
#define RX_THD_NUM						0
#define TX_THD_NUM						0
#define INTER_ME_SIG_NUM				15
#define SIG_INIT_DONE_TO_XSCALE_ADDR	0x4004
#define PATTERN_INIT_DONE_TO_XSCALE		0xCBCBCBCB
#define BUFFER_ADDR_MASK				0xFFFFFF

.reg $TransferReg00 $TransferReg01
.reg temp
.reg RxThreadList RxUPControl0 elem
.reg RxConfigData $RxConfigData0 RxConfigData0
.reg rbuf
.reg MsfAddress MsfAddress0 MsfAddress1 MsfAddress2
.sig msf_sig
.sig rx_sig_thd

.set $TransferReg00

br=ctx[0, here#]
ctx_arb[kill]

here#:

context_enable_csr_config#:
//**********************************************************
// Program CSR Context Enables, used by the context arbiter
//**********************************************************

// Initialize CTX_Enables CSR (Put into 8 CTX mode) 
// Bit 31: In-Use contexts: 0 = 8 ctx mode, 1 = 4 ctx mode
// Bit 20: Next Neigher registers are written from this ME
// Bit  17, 1=LM_ADDR_1 is GLOBAL, 0=LM_ADDR_1 is context_relative
// Bit  16, 1=LM_ADDR_0 is GLOBAL, 0=LM_ADDR_0 is context_relative
// Bits [15:8] CTX enables for contexts 7:0

#define In_Use_Contexts				0
#define Control_Store_Parity_Error	0
#define Control_Store_Parity_Enable	0
#define Breakpoint					0
#define NN_Mode						1
#define NN_Ring_Empty				0
#define LM_ADDR_1_Global			0
#define	LM_ADDR_0_Global			0

#define Enable						0xff


//****************************************************
// Configure RX/TX Control
//****************************************************
	immed[RxConfigData0, ((0<<9) | (RX_ELEMENTSIZE << 2))]
	immed_w1[RxConfigData0, ((RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
	alu[$RxConfigData0, --, B, RxConfigData0]
	immed[MsfAddress, MSF_RX_CONTROL]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


//******************************************************
// Initialize RBUF Freelist to add elements to the list
//******************************************************
.begin
	.reg temp_reg

	immed[temp_reg, 0]

init_RBUF#:
	alu[temp, --, B, temp_reg, <<16]
	msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]
	alu[temp_reg, temp_reg, +, 1]
	alu[--, RBUF_ELEM_COUNT, -, temp_reg]
	bne[init_RBUF#]
.end


//******************************************************
// Configure RX UP Control CSRs 
//******************************************************
	immed[RxUPControl0, (UP_CTRL_PP_MODE | UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
	alu[$RxConfigData0, --, B, RxUPControl0]
	immed[MsfAddress2, RX_UP_CONTROL_0]
	msf[write, $RxConfigData0, MsfAddress2, 0, 1], ctx_swap[msf_sig]

	immed[RxConfigData0, ((0<<9) | (RX_ELEMENTSIZE << 2))]
	immed_w1[RxConfigData0, ((RX_ENABLE_MASK << 12) | (RX_MODE << 6) | (RX_WIDTH << 4) | (RX_SINGLE_PHY << 3) | (0<<1)|(0<<0))]
	alu[$RxConfigData0, --, B, RxConfigData0]
	immed[MsfAddress, MSF_RX_CONTROL]
	msf[write, $RxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


//*******************************************
// Configure Ctx_Enables
//*******************************************
.begin
	.reg CtxEnableData

	immed[CtxEnableData, (Enable << 8)]
	immed_w1[CtxEnableData, ((In_Use_Contexts << 15)|(Control_Store_Parity_Error << 13)|(Control_Store_Parity_Enable << 12)|(Breakpoint << 11)|(NN_Mode << 4)|(NN_Ring_Empty << 2)|(LM_ADDR_1_Global << 1)|(LM_ADDR_0_Global << 0))]
	local_csr_wr[CTX_Enables, CtxEnableData]
.end


//********************************************************
// Start of Test	
//********************************************************

start#:
	.xfer_order $TransferReg00 $TransferReg01


//*******************************************************
// Configure RX Thread List CSRs             
// add thread id to free list and wait on signal
//*******************************************************
InitStart#:
.begin
	.reg cur_me, cur_ctx
	local_csr_rd[ACTIVE_CTX_STS]
	immed[temp, 0]
	alu[cur_me, 0xF, AND, temp, >>3]	// Extract the current ME number
	alu[cur_ctx, 0x7, AND, temp]		// Extract the current context number
	immed[RxThreadList, (RX_SIGNAL_THREAD << 12)]
	alu[RxThreadList, RxThreadList, OR, cur_me, <<7]
	alu[RxThreadList, RxThreadList, OR, cur_ctx, <<4]
.end

Init_Common#:
	immed[rbuf, RBUF_TBUF ]
	immed[MsfAddress0, RX_THREAD_FREELIST_0]
	immed[MsfAddress1, RBUF_ELEMENT_DONE]
	alu[RxConfigData, RxThreadList,  OR , RX_TRANSFER_THREAD]
	alu[RxConfigData, --,  B, RxConfigData, <<16]		// For msf[fast_wr...]


ReceivePacket#:
	.set_sig rx_sig_thd
	msf[fast_wr, --, MsfAddress0, RxConfigData] // add thread to freelist
	ctx_arb[rx_sig_thd]
	
RSW#:
	alu_shf[elem, --, B, $TransferReg00, >>24]	// Get element number

//**************************************************************
//  Free up Element by writing to RBUF_Element_Done{Channel} 3
//**************************************************************
//	local_csr_wr[SAME_ME_SIGNAL, SIG_CTX]
	alu[temp, --, B, elem, <<16]
	msf[fast_wr, --, temp, RBUF_ELEMENT_DONE]

NULL#:
next_packet#:
	// loop around and wait for next packet
	br[ReceivePacket#]