📄 crc_diag.c
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/* crc_diag.c
*
*-------------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*-------------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: chinmay, NOVEMBER, 2002
*
*
* ------------------------------------------------------------------------------
*/
typedef unsigned long ulong;
typedef unsigned short ushort;
#include "common.h"
#include "memory.h"
#include "msf_common.h"
#include "diagstruct.h"
#include "led.h"
#include "uc_load.h"
#include "pci_diag.h"
#include "pci.h"
#include "hal_ixdp2400.h"
#include "memory.h"
#include "syslog.h"
#include "uart.h"
#include "msf_init.h"
#include "diag_utils.h"
#include "error_code.h"
#include "error_map.h"
#include "reg_api.h"
#include "register_map.h"
#include "diag.h"
#include "dp_proto.h"
#include "mac_util.h"
#include "mac_init.h"
#define LEN64_PKTS 3 /* expected 64 byte packets, per port */
#define LEN96_PKTS 3 /* expected 96 byte packets, per port */
#define LEN138_PKTS 3 /* expected 138 packets, per port */
#define EXP_BAD_PKTS 0 /* expected dropped packets, per port */
#define CHECK64 0x00 /* This is the 1st byte of the unicast frame */
#define CHECK96 0xB1 /* This is the 1st byte of the multicast frame */
#define CHECK138 0xFF /* This is the 1st byte of the broadcast frame */
#define ILLEGAL_CRC_APPEND 0xBAD6
#define ILLEGAL_CRC_STRIP 0xBAD7
#define CRC_STRIP_FAILED 0xBAD8
#define CRC_APPEND_FAILED 0xBAD9
extern const int pl_sys_loopback_eg_rx[];
extern const int pl_sys_loopback_eg_tx[];
extern const int pl_sys_loopback_in_rx[];
extern const int pl_sys_loopback_in_tx[];
extern pci_device slave_dev_info; // for slave npu info.
extern UINT32 PKT_96_SZ,PKT_64_SZ,PKT_138_SZ;
extern UINT32 PKT_SEQ_SZ,ALL_PORT_PKT_SEQ_SZ;
extern UINT32 Sz_pl_sys_loopback_eg_rx;
extern UINT32 Sz_pl_sys_loopback_eg_tx;
extern UINT32 Sz_pl_sys_loopback_in_rx;
extern UINT32 Sz_pl_sys_loopback_in_tx;
extern UINT32 *pl_sys_lb_data96_0;
extern UINT32 *pl_sys_lb_data64_0;
extern UINT32 *pl_sys_lb_data138_0;
extern UINT32 *pl_sys_lb_data96_1;
extern UINT32 *pl_sys_lb_data64_1;
extern UINT32 *pl_sys_lb_data138_1;
extern UINT32 *pl_sys_lb_data96_2;
extern UINT32 *pl_sys_lb_data64_2;
extern UINT32 *pl_sys_lb_data138_2;
extern UINT32 *pl_sys_lb_data96_3;
extern UINT32 *pl_sys_lb_data64_3;
extern UINT32 *pl_sys_lb_data138_3;
extern UINT32 tx_data_pl[];
extern UINT32 tx_data_pl_0[];
extern UINT32 tx_data_pl_1[];
extern UINT32 tx_data_pl_2[];
extern UINT32 tx_data_pl_3[];
extern UINT32 data64_0[];
extern UINT32 data64_1[];
extern UINT32 data64_2[];
extern UINT32 data64_3[];
extern UINT32 data96_0[];
extern UINT32 data96_1[];
extern UINT32 data96_2[];
extern UINT32 data96_3[];
extern UINT32 data138_0[];
extern UINT32 data138_1[];
extern UINT32 data138_2[];
extern UINT32 data138_3[];
extern UINT32 rxport[4];
/** globals **/
extern UINT32 total_args,loop,ports,speed;
extern char channel,test_opt;
extern UINT8 test_param;
extern UINT32 validate_params(void);
extern UINT32 init_mac_dev(UINT32);
extern void Set_Pci_Doorbell(int bit_num, int db_intr_addr);
short Count64[4],Count96[4],Count138[4];
int get_crctest_stats(short);
// ******************************************************************************
// Function: void crc_test(void)
//
// This function is called by the Test Manager when the user invokes the
// point Lone system crc test
// ******************************************************************************
UINT32 crc_test(void)
{
UINT32 ctr, flag, slave_mailbox0_addr, pkt_size, status, tx_count=0, rx_count=0;
UINT32 scratch_ring_tx_count, scratch_ring_rx;
UINT32 dcache_status, forever = 0, combination, port_num, rx_port_num;
UINT32 loop_count=0;
UINT32 *pl_sys_lb_data=0;
UINT32 scratch_read_value=0, dram_addr, orig_data_size=0;
volatile int mailbox_value, temp;
register PDiagCommon acL = (PDiagCommon) ACADDRESS;
short crcError=0;
UINT32 pass_port[4],rxflag[4];
UINT32 expected_num_pkts = 0,iteration = 0, port_ctr=0, pnum=0, *pktptr=0;
UINT32 exp_pkt_sz = 0,cflag = 0;
UINT32 bad_pkt_size = 0;
UINT32 counter=0;
channel = 'f';
total_args = acL->argc;
test_opt = acL->argv[2][0];
test_param = acL->argv[3][0];
channel = acL->argv[4][0];
speed = acL->decArg[5];
ports = acL->decArg[6];
loop = acL->decArg[7];
if (validate_params() == INVALID_PARAMETERS)
{
eprintf("Invalid parameters. \n");
return INVALID_PARAMETERS;
}
if (channel == 'c')
{
cflag = 1;
}
if (total_args <= 7)
{
loop = 1;
}
if (loop == 0)
{
forever = 1;
}
else
{
forever = 0;
}
/* initialize port array to 0 */
for (ctr = 0;ctr<4;ctr++)
{
pass_port[ctr] = 0;
rxflag[ctr] = ERROR;
/* initialize packet counts to 0 */
Count64[ctr]=0;
Count96[ctr]=0;
Count138[ctr]=0;
}
/* get the packet data used specifically for the test */
get_packets_for_filter_test();
switch(ports)
{
case 0: pktptr = tx_data_pl_0;
pnum = PKT_SEQ_SZ/4;
iteration = 1;
break;
case 1: pktptr = tx_data_pl_1;
pnum = PKT_SEQ_SZ/4;
iteration = 1;
break;
case 2: pktptr = tx_data_pl_2;
pnum = PKT_SEQ_SZ/4;
iteration = 1;
break;
case 3: pktptr = tx_data_pl_3;
pnum = PKT_SEQ_SZ/4;
iteration = 1;
break;
case 4: pktptr = tx_data_pl;
pnum = ALL_PORT_PKT_SEQ_SZ/(4*4);
if (cflag)
iteration = 2;
else
iteration = 4;
break;
}
scratch_ring_rx = SCR_RING_INSTR_ADDR + (5 << 2);
scratch_ring_tx_count = SCR_RING_INSTR_ADDR + (4 << 2);
if(acL->HostType == MASTER) // if master NPU
{
flag = OK;
Msf_OutOfReset();
status = Msf_PLL();
if (status == ERROR)
{
return ABORT;
}
eprintf("Initialising media card. Please wait...\n");
status = init_mac_dev(0);
if (status != DONE)
{
eprintf("Aborting Test\n");
return ABORT;
}
clear_stat_regs();
spConfig();
switch(test_param)
{
case 'a': /* test for CRC Append */
eprintf("Testing CRC append ...\n");
//reg_write((RXFIFO_DROP_ENABLE),0xF);
for(port_ctr=0; port_ctr<NUM_PORTS;port_ctr++)
{
/*enable CRC append */
reg_write((DIV_CONFIG_WORD+(port_ctr*PORTSZ)),0x114D);
/* enable CRC strip */
reg_write(RXFIFO_PAD_CRCSTRIP_ENB, 0xF0);
}
break;
case 'd': /* disable crc append and crc strip */
case '4': /* test for RMON regs: Rx FCSErrors and Tx CRC Errors */
//reg_write((RXFIFO_DROP_ENABLE),0xF);
for(port_ctr=0; port_ctr<NUM_PORTS;port_ctr++)
{
if (!cflag)
/*disable CRC append */
reg_write((DIV_CONFIG_WORD+(port_ctr*PORTSZ)),0x112D);
else
reg_write((DIV_CONFIG_WORD+(port_ctr*PORTSZ)),0x110D);
/* disable CRC strip */
reg_write(RXFIFO_PAD_CRCSTRIP_ENB, 0x00);
}
break;
default :
eprintf("Invalid parameters. \n");
return INVALID_PARAMETERS;
}
spRestore();
eprintf("Media card initialisation completed.\n");
dcache_status = get_CP15() & DCACHE_BIT;
if(dcache_status != 0) // if dcache ON
{
dcache_off();
}
*(PCI_ADDR_EXT_REG) = (slave_dev_info.base_address[CSR_BAR] & 0xE0000000) >> 16;
slave_mailbox0_addr = slave_dev_info.base_map[CSR_BAR] + PCI_CSR_BASE_FRM_PCI + MAILBOX_0_OFF;
PUT32(slave_mailbox0_addr, 0);
#ifdef __ARMEB__
PUT32((slave_dev_info.base_map[CSR_BAR] + PCI_CSR_BASE_FRM_PCI + MAILBOX_3_OFF), SWAP32(1));
#else
PUT32((slave_dev_info.base_map[CSR_BAR] + PCI_CSR_BASE_FRM_PCI + MAILBOX_3_OFF), 1);
#endif
PUT32((SCRATCHPAD_BASE + SCRATCH_MSG_BASE), DRAM_BASE_SRC);
// Write packet data to DRAM for microcode to use
for (ctr = 0; ctr < PKT_96_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_96_0 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data96_0[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_64_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_64_0 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data64_0[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_138_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_138_0 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data138_0[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_96_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_96_1 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data96_1[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_64_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_64_1 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data64_1[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_138_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_138_1 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data138_1[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_96_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_96_2 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data96_2[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_64_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_64_2 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data64_2[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_138_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_138_2 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data138_2[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_96_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_96_3 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data96_3[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_64_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_64_3 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data64_3[(ctr / 4)]);
}
for (ctr = 0; ctr < PKT_138_SZ; ctr+=4)
{
PUT32((DRAM_BASE_SRC + ((RING_DATA_138_3 >> 8) & (MASK_16BIT << 8)) + ctr), pl_sys_lb_data138_3[(ctr / 4)]);
}
PUT32((PCI_LOCAL_CSR_BASE + MAILBOX_0_OFF), 0);
// pkt_size = PACKET_SIZE;
// Invoke the slave's PCI doorbell
Set_Pci_Doorbell(PTLONE_SYS_LPBK, (slave_dev_info.base_map[CSR_BAR] + PCI_CSR_BASE_FRM_PCI + XSCALE_DOORBELL_OFF));
ctr = 0;
// Wait for a signal that slave NPU has completed loading of ucode and init
do
{
if (ctr == 1500) // After 10 seconds
{
eprintf("\nTimed out...Slave NPU was not able to load microcode and init.\n");
mailbox_value = INIT_ERROR;
flag = ERROR;
break;
}
temp = GET32(slave_mailbox0_addr);
hal_delay_us(10000);
ctr++;
}
while (temp == 0);
if (flag == OK) // If slave completed microcode loading successfully
{
// Load Master's NPU with ucode and init
DownLoadUcode(PL_SYS_LOOPBACK_EG_TX_ME, Sz_pl_sys_loopback_eg_tx, (UINT32 *)pl_sys_loopback_eg_tx);
DownLoadUcode(PL_SYS_LOOPBACK_EG_RX_ME, Sz_pl_sys_loopback_eg_rx, (UINT32 *)pl_sys_loopback_eg_rx);
hal_delay_us(1000000);
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