📄 mac_util.c
字号:
bad_option = 0;
break;
case 's': mac_test_flag |= SPI3_TEST_MASK;
bad_option = 0;
break;
case 'w': mac_test_flag |= POWDN_TEST_MASK;
bad_option = 0;
break;
case 'e': mac_test_flag |= RESET_TEST_MASK;
bad_option = 0;
break;
case 'z': mac_test_flag |= FRSZ_TEST_MASK;
bad_option = 0;
break;
case 'l': mac_test_flag |= LED_TEST_MASK;
bad_option = 0;
break;
case 'k': mac_test_flag |= WMARK_TEST_MASK;
bad_option = 0;
break;
case '?': show_options_help();
break;
default:
//eprintf("bad test option: %c\n",test_opt);
show_options_help();
//return INVALID_PARAMETERS;
break;
}
}
static void show_options_help(void)
{
short i=0;
eprintf("Mac test options\n");
eprintf("----------------\n");
for (i=0;i<aTestHelpSz;i++)
{
eprintf("%s\n",aTestHelp[i]);
}
}
UINT32 do_mac_test(void)
{
char saddr[5],sval[10];
short i=0;
unsigned int address = 0,value=0;
switch (mac_test_flag)
{
case PHY_REG_WRITE:
phy_write();
break;
case PHY_READ_ALL:
spConfig();
gbe_mac_phy_read_all();
spRestore();
break;
case RD_ALL_REGS:
read_all_regs();
break;
case REG_RD:
spConfig();
/*** read vallejo registers ***/
eprintf("\nEnter Vallejo Reg. offset :");
for (i=0;i<=4;i++)
saddr[i] = '\0';
i=0;
gets(saddr, 4);
address=htoi(saddr);
eprintf("\nReading offset 0x%08X, value = 0x%08X\n",address,reg_read(address));
strcpy(saddr,"00000");
spRestore();
break;
case REG_WR:
spConfig();
/*** read vallejo registers ***/
eprintf("\nEnter Vallejo Reg. offset :");
for (i=0;i<=4;i++)
saddr[i] = '\0';
i=0;
gets(saddr, 4);
eprintf("\nEnter Value :");
gets(sval, 9);
address = htoi(saddr);
value = htoi(sval);
reg_write(address,value);
eprintf("writing offset 0x%x, value = 0x%x\n",address,value);
strcpy(saddr,"00000");
strcpy(sval,"000000000");
spRestore();
break;
case ADR_FILTER_MASK:
/*
* invoke MAC address filtering diagnostic tests
*/
mac_address_filter_test();
break;
case SPI3_TEST_MASK:
/*
* invoke spi-3 diagnostic tests
*/
spi3_test();
break;
case RMON_TEST_MASK:
/*
* invoke diagnostic tests for Rx statistic registers.
*/
rmon_test();
break;
case PERPORT_TEST_MASK:
/*
* invoke diagnostic tests for per port registers.
*/
per_port_reg_test();
break;
case I2C_TEST_MASK:
/*
* invoke I2C diagnostic tests
*/
i2c_test ();
break;
case CRC_TEST_MASK:
/*
* invoke CRC diagnostic tests
*/
crc_test();
break;
case MDIO_TEST_MASK:
/*
* invoke mdio diagnostic tests
*/
mdio_config_test (); /* mdio config register diagnostics */
//mdc_speed_test (); /* mdio clock speed test */
break;
case PAD_TEST_MASK:
/*
* invoke Rx/Tx fifo padding diagnostic tests
*/
padding_test();
break;
case VLPSE_TEST_MASK:
/*
* invoke VLAN and PAUSE frame diagnostic tests
*/
vlan_pause_filter_test();
break;
case POWDN_TEST_MASK:
/*
* invoke fifo powerdown diagnostic tests
*/
powerDown_test();
break;
case RESET_TEST_MASK:
/*
* invoke reset diagnostic tests
*/
reset_test();
break;
case FRSZ_TEST_MASK:
/*
* invoke frame size diagnostic tests
*/
frame_size_test();
break;
case LED_TEST_MASK:
/*
* invoke LED diagnostic tests
*/
led_test();
break;
case WMARK_TEST_MASK:
/*
* invoke fifo watermark diagnostic tests
*/
wmark_test();
break;
} /* end of switch */
/* reset the mac test flag */
mac_test_flag = 0;
return DONE;
}
UINT32 validate_params()
{
short fault=0;
switch(channel)
{
case 'f':
if (speed != 1000)
{
eprintf("Invalid speed parameter for fiber channels. It should be 1000.\n");
fault = 1;
}
break;
case 'c':
if ((speed != 10) && (speed != 100) && (speed != 1000))
{
eprintf("Invalid speed selected for copper channels\n");
fault = 1;
}
break;
default:
eprintf("Invalid Channel Mode\n");
show_options_help();
fault = 1;
break;
}
if ((ports < 0) || (ports > 4))
{
eprintf("Invalid port number\n");
fault = 1;
}
if (fault)
return INVALID_PARAMETERS;
if (loop == 0)
{
eprintf("Loopback test executed for infinite packets..\n");
eprintf("Please press a key to stop test ..\n");
}
return 0;
}
UINT32 assign_pkt_pointers(UINT32 ports, UINT32 *pktptr, UINT32 cflag, UINT32 *pnum)
{
short iteration=0;
switch(ports)
{
case 0: pktptr = tx_data_pl_0;
*pnum = PKT_SEQ_SZ/4;
iteration = 1;
break;
case 1: pktptr = tx_data_pl_1;
*pnum = PKT_SEQ_SZ/4;
iteration = 1;
break;
case 2: pktptr = tx_data_pl_2;
*pnum = PKT_SEQ_SZ/4;
iteration = 1;
break;
case 3: pktptr = tx_data_pl_3;
*pnum = PKT_SEQ_SZ/4;
iteration = 1;
break;
case 4: pktptr = tx_data_pl;
*pnum = ALL_PORT_PKT_SEQ_SZ/(4*4);
if (cflag)
iteration = 2;
else
iteration = 4;
break;
}
return iteration;
}
short check_autoneg_status(void)
{
short s_PortCount = 0, flag = OK, ctr = 0, done = 0;
UINT32 regval = 0, link=0,receiver_status=0, autoneg_complete=0;
register PDiagCommon acL = (PDiagCommon) ACADDRESS;
short port;
port = acL->decArg[6];
eprintf("Waiting for auto-negotiation to complete ....\n");
for(s_PortCount=0; s_PortCount<4; s_PortCount++)
{
if ((s_PortCount == port) || (port == 4))
{
do
{
switch(speed)
{
case 1000:
regval = gbe_mac_phy_read(s_PortCount,0xA);
link = gbe_mac_phy_read(s_PortCount,0x11);
link = (link >> 12) & 0x1;
receiver_status = (regval >> 12) & 0x3;
//eprintf("receiver status = 0x%x\n",receiver_status);
if (receiver_status == 0x3)
done = 1;
break;
case 100:
//regval = gbe_mac_phy_read(s_PortCount,0xA);
link = gbe_mac_phy_read(s_PortCount,0x01);
link = (link >>2) & 1;
done = 1;
break;
case 10:
//regval = gbe_mac_phy_read(s_PortCount,0xA);
link = gbe_mac_phy_read(s_PortCount,0x16);
done = gbe_mac_phy_read(s_PortCount,0x01);
link = (link >> 6) & 1;
done = (done >> 2) & 1;
break;
}
//eprintf("Regval for port %d = 0x%08X\n",s_PortCount,regval);
//receiver_status = (regval >> 12) & 0x3;
autoneg_complete = gbe_mac_phy_read(s_PortCount,0x1);
if ((((autoneg_complete >> 5) & 1) == 0x1) && (link == 1) && done)
{
flag = OK;
break;
}
else
{
ctr ++;
flag = ERROR;
}
}while (ctr < 200);
if (flag == ERROR)
{
eprintf("Auto-negotiation failed for port %d , link = 0x%08X, auto = 0x%08X\n",s_PortCount,link, autoneg_complete);
}
}
}
return flag;
}
UINT32 cu_init(UINT32 set_int_lpbk)
{
int port;
if (config_phy() == ABORT)
return ABORT;
/* apply reset to MAC device */
mac_reset_config();
reg_write(PORT_ENABLE,0x0);
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(SERDES_CLKMODE_REG,0xf);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(PORT_ENABLE,0x0);
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(INTERFACE_MODE,0xF); /** enable copper mode **/
switch(dplx)
{
case 'h' :
reg_write(DESIRED_DUPLEX,0x0);
reg_write(DESIRED_DUPLEX+INDEX_PORT1,0x0);
reg_write(DESIRED_DUPLEX+INDEX_PORT2,0x0);
reg_write(DESIRED_DUPLEX+INDEX_PORT3,0x0);
break;
case 'f' :
reg_write(DESIRED_DUPLEX,0x1);
reg_write(DESIRED_DUPLEX+INDEX_PORT1,0x1);
reg_write(DESIRED_DUPLEX+INDEX_PORT2,0x1);
reg_write(DESIRED_DUPLEX+INDEX_PORT3,0x1);
break;
default :
eprintf("Illegal duplex optinon.\n");
eprintf("The opertation will be full duplex..\n");
break;
}
reg_write(SERDES_CLKMODE_REG,0xF);
reg_write(SPI3_TX_GLOBAL_CONFIG,0x20aa0f);
reg_write(SPI3_RX_CONFIG, 0xAA0F80);
reg_write(DIV_CONFIG_WORD,0x114D);
reg_write(DIV_CONFIG_WORD+INDEX_PORT1,0x114D);
reg_write(DIV_CONFIG_WORD+INDEX_PORT2,0x114D);
reg_write(DIV_CONFIG_WORD+INDEX_PORT3,0x114D);
reg_write(0x5B3,0xF0);
reg_write(SERDES_CLKMODE_REG,0x0);
if (speed == 100)
{
reg_write(MAC_IF_MODE,0x5);
reg_write(MAC_IF_MODE+INDEX_PORT1,0x5);
reg_write(MAC_IF_MODE+INDEX_PORT2,0x5);
reg_write(MAC_IF_MODE+INDEX_PORT3,0x5);
}
if (speed == 10)
{
reg_write(MAC_IF_MODE,0x4);
reg_write(MAC_IF_MODE+INDEX_PORT1,0x4);
reg_write(MAC_IF_MODE+INDEX_PORT2,0x4);
reg_write(MAC_IF_MODE+INDEX_PORT3,0x4);
}
if (speed == 1000)
{
reg_write(MAC_IF_MODE,0x6);
reg_write(MAC_IF_MODE+INDEX_PORT1,0x6);
reg_write(MAC_IF_MODE+INDEX_PORT2,0x6);
reg_write(MAC_IF_MODE+INDEX_PORT3,0x6);
}
reg_write(SERDES_CLKMODE_REG,0xF);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(TXFIFO_PAD_ENB,0xAAAA);
reg_write(SERDES_TX_RX_POW_DOWN,0x0);
mac_config();
reg_write(GBIC_CTRL_REG,0x1C00);
reg_write(LED_MODE, 0x3);
// Activate units
reg_write(0x505, 0x0); // MAC Soft reset
reg_write(0x506, 0x0); // MDIO Reset
reg_write(0x620, 0x0); // TX FIFO Reset
reg_write(0x59E, 0x0); // Rx FIFO Reset
//mac_disable_reset();
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(SERDES_CLKMODE_REG,0xf);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(PORT_ENABLE,0xF);
// fix for CRC error @ 1G
for(port = 0; port < 4; port++)
{
gbe_mac_phy_write(port, 22, 0x2018);
gbe_mac_phy_write(port, 24, 0x3248);
}
return DONE;
}
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