📄 mac_init.c
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switch(dplx)
{
/* chinmay: only Cu ports can be in half duplex mode */
case 'h' : /* reg_write(DESIRED_DUPLEX,0x0);
reg_write(DESIRED_DUPLEX+INDEX_PORT1,0x0);*/
reg_write(DESIRED_DUPLEX+INDEX_PORT2,0x0);
reg_write(DESIRED_DUPLEX+INDEX_PORT3,0x0);
break;
case 'f' :
reg_write(DESIRED_DUPLEX+INDEX_PORT2,0x1);
reg_write(DESIRED_DUPLEX+INDEX_PORT3,0x1);
break;
default : eprintf("Illegal duplex optinon.\n");
eprintf("The opertation will be full duplex..\n");
break;
}
/* For mixed mode, fiber ports must always be in full duplex */
reg_write(DESIRED_DUPLEX+INDEX_PORT0,0x1);
reg_write(DESIRED_DUPLEX+INDEX_PORT1,0x1);
reg_write(SERDES_CLKMODE_REG,0xF);
#ifdef SPHY4x8
reg_write(SPI3_TX_GLOBAL_CONFIG,0x20aa0f);
#else
reg_write(SPI3_TX_GLOBAL_CONFIG,0x00aa0f);
#endif
reg_write(DIV_CONFIG_WORD,0x116D);
reg_write(DIV_CONFIG_WORD+INDEX_PORT1,0x116D);
reg_write(DIV_CONFIG_WORD+INDEX_PORT2,0x114D); // Fibre
reg_write(DIV_CONFIG_WORD+INDEX_PORT3,0x114D); // Fibre
reg_write(0x5B3,0xF0);
reg_write(SERDES_CLKMODE_REG,0x0);
if (speed == 100)
{
//reg_write(MAC_IF_MODE,0x5);
//reg_write(MAC_IF_MODE+INDEX_PORT1,0x5);
reg_write(MAC_IF_MODE+INDEX_PORT2,0x5);
reg_write(MAC_IF_MODE+INDEX_PORT3,0x5);
}
if (speed == 10)
{
// reg_write(MAC_IF_MODE,0x4);
// reg_write(MAC_IF_MODE+INDEX_PORT1,0x4);
reg_write(MAC_IF_MODE+INDEX_PORT2,0x4);
reg_write(MAC_IF_MODE+INDEX_PORT3,0x4);
}
if (speed == 1000)
{
// reg_write(MAC_IF_MODE,0x6);
// reg_write(MAC_IF_MODE+INDEX_PORT1,0x6);
reg_write(MAC_IF_MODE+INDEX_PORT2,0x6);
reg_write(MAC_IF_MODE+INDEX_PORT3,0x6);
}
reg_write(SERDES_CLKMODE_REG,0xF);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(TXFIFO_PAD_ENB,0xAAAA);
reg_write(GBIC_CTRL_REG,0x1C00);
reg_write(LED_MODE, 0x3);
// Activate units
reg_write(0x505, 0x0); // MAC Soft reset
reg_write(0x506, 0x0); // MDIO Reset
reg_write(0x620, 0x0); // TX FIFO Reset
reg_write(0x59E, 0x0); // Rx FIFO Reset
mac_disable_reset();
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(SERDES_CLKMODE_REG,0xf);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(PORT_ENABLE,0xF);
}
short check_autoneg_status_mixed_mode()
{
short s_PortCount = 0, flag = OK, ctr = 0, done = 0;
UINT32 regval = 0, link=0,receiver_status=0, autoneg_complete=0;
eprintf("Waiting for auto-negotiation to complete ....\n");
for(s_PortCount=cport; s_PortCount<(cport+2); s_PortCount++)
{
do
{
switch(speed)
{
case 1000:
regval = gbe_mac_phy_read(s_PortCount,0xA);
link = gbe_mac_phy_read(s_PortCount,0x11);
link = (link >> 12) & 0x1;
receiver_status = (regval >> 12) & 0x3;
//eprintf("receiver status = 0x%x\n",receiver_status);
if (receiver_status == 0x3)
{
done = 1;
}
break;
case 100:
//regval = gbe_mac_phy_read(s_PortCount,0xA);
link = gbe_mac_phy_read(s_PortCount,0x01);
link = (link >>2) & 1;
done = 1;
break;
case 10:
//regval = gbe_mac_phy_read(s_PortCount,0xA);
link = gbe_mac_phy_read(s_PortCount,0x16);
done = gbe_mac_phy_read(s_PortCount,0x01);
link = (link >> 6) & 1;
done = (done >> 2) & 1;
break;
}
//eprintf("Regval for port %d = 0x%08X\n",s_PortCount,regval);
//receiver_status = (regval >> 12) & 0x3;
autoneg_complete = gbe_mac_phy_read(s_PortCount,0x1);
if ((((autoneg_complete >> 5) & 1) == 0x1) && (link == 1) && done)
{
flag = OK;
break;
}
else
{
ctr ++;
flag = ERROR;
}
}while (ctr < 5000);
if (flag == ERROR)
{
eprintf("Auto-negotiation failed for port %d , link = 0x%08X, auto = 0x%08X\n",s_PortCount,link, autoneg_complete);
}
}
return flag;
}
void read_all_regs()
{
int c=0;
int port_offset = 0;
int i=0;
register PDiagCommon acL = (PDiagCommon) ACADDRESS;
if(acL->argv[3][0] == 's')
{
media_seat = 0xBABECAFE;
}
spConfig();
eprintf("offset \t value\n");
eprintf("MAC control registers ----\n");
for (i=0;i<=3;i++)
{
eprintf("port %d ----\n",i);
for (c=0;c<=0x1B;c++)
{
eprintf("0x%x \t 0x%x\n", c, reg_read(port_offset+c));
}
port_offset = port_offset + 0x80;
}
port_offset = 0;
eprintf("RX stat registers -- \n");
for (i=0;i<=3;i++)
{
eprintf("port %d ----\n",i);
for (c=0x20;c<=0x39;c++)
{
eprintf("0x%x \t 0x%x\n", c, reg_read(port_offset+c));
}
port_offset = port_offset + 0x80;
}
port_offset = 0;
eprintf("TX stat registers -- \n");
for (i=0;i<=3;i++)
{
eprintf("port %d ----\n",i);
for (c=0x40;c<=0x58;c++)
{
eprintf("0x%x \t 0x%x\n", c, reg_read(port_offset+c));
}
port_offset = port_offset + 0x80;
}
port_offset = 0;
eprintf("PHY autoscan registers -- \n");
for (i=0;i<=3;i++)
{
eprintf("port %d ----\n",i);
for (c=0x60;c<=0x7F;c++)
{
eprintf("0x%x \t 0x%x\n", c, reg_read(port_offset+c));
}
port_offset = port_offset + 0x80;
}
eprintf("Global status and config registers -- \n");
for (c=0x500;c<=0x50c;c++)
{
eprintf("0x%x \t 0x%x\n",c,reg_read(c));
}
eprintf("RX FIFO registers -- \n");
for (c=0x580;c<=(0x580+0x3f);c++)
{
eprintf("0x%x \t 0x%x\n",c,reg_read(c));
}
eprintf("TX FIFO registers -- \n");
for (c=0x600;c<=0x63e;c++)
{
eprintf("0x%x \t 0x%x\n",c,reg_read(c));
}
eprintf("MDIO registers -- \n");
for (c=0x680;c<=0x683;c++)
{
eprintf("0x%x \t 0x%x\n",c,reg_read(c));
}
eprintf("SPI-3 registers -- \n");
for (c=0x700;c<=0x716;c++)
{
eprintf("0x%x \t 0x%x\n",c,reg_read(c));
}
eprintf("Serdes registers -- \n");
for (c=0x780;c<=(0x780 + 0x18);c++)
{
eprintf("0x%x \t 0x%x\n",c,reg_read(c));
}
eprintf("GBIC registers -- \n");
for (c = (0x780 + 0x19); c <= (0x780 + 0x1B); c++)
{
eprintf("0x%x \t 0x%x\n", c, reg_read(c));
}
eprintf("PLL tune registers -- \n");
for (c = (0x780 + 0x1C); c <= (0x780 + 0x1E); c++)
{
eprintf("0x%x \t 0x%x\n", c, reg_read(c));
}
eprintf(" -- Read complete -- \n");
spRestore();
media_seat = 0;
}
void spConfig()
{
Disable_CPSR_Int();
orig_sp_val[0] = GET32(0xC0080000);
orig_sp_val[1] = GET32(0xC0080004);
orig_sp_val[2] = GET32(0xC0080008);
orig_sp_val[3] = GET32(0xC008000C);
orig_sp_val[4] = GET32(0xC0080010);
orig_sp_val[5] = GET32(0xC0080014);
orig_sp_val[6] = GET32(0xC0080018);
orig_sp_val[7] = GET32(0xC008001C);
if(((silicon_rev & 0xF0) >> 4))
{
//PUT32(0xC0080000, 0x6);
PUT32(0xC0080000, 0xD);
}
else
{
PUT32(0xC0080000, 0x2);
}
PUT32(0xC0080008, 0x62);
PUT32(0xC0080010, 0x62);
PUT32(0xC0080018, 0x3);
PUT32(0xC008001C, 0x33);
Enable_CPSR_Int();
}
void spRestore()
{
Disable_CPSR_Int();
PUT32(0xC0080000, orig_sp_val[0]);
PUT32(0xC0080004, orig_sp_val[1]);
PUT32(0xC0080008, orig_sp_val[2]);
PUT32(0xC008000C, orig_sp_val[3]);
PUT32(0xC0080010, orig_sp_val[4]);
PUT32(0xC0080014, orig_sp_val[5]);
PUT32(0xC0080018, orig_sp_val[6]);
PUT32(0xC008001C, orig_sp_val[7]);
Enable_CPSR_Int();
}
int ctoi(char c)
{
int j=0;
if ((c >= '0') && (c <= '9')) // check if number
{
j = c - '0';
}
else
if ((c >= 'a') && (c <= 'f'))
{
j = c - 'a' + 10;
}
return j;
}
unsigned int htoi(char *s)
{
unsigned int number = 0,temp=1;
unsigned int len=0,i=1;
char *t=s;
while (*s++ != 0)
len++;
while(i<len)
{
temp = temp * 16;
i++;
}
i=0;
while (t[i] != '\0')
{
number = number + (temp*ctoi(t[i]));
i++;
temp = temp/16;
}
return number;
}
void phy_write()
{
char p_addr[3],val[10];
UINT32 address=0;
UINT32 value=0;
UINT32 port=0;
spConfig();
eprintf("Enter phy reg address :\n");
gets(p_addr,4);
eprintf("Enter value :\n");
gets(val,9);
address=htoi(p_addr);
value=htoi(val);
for(port=0; port<4;port++)
{
gbe_mac_phy_write(port, address, value);
}
spRestore();
}
void get_stats()
{
UINT32 port_offset=0;
short i=0,c=0;
spConfig();
for (i=0;i<=3;i++)
{
for (c=0x20;c<=0x39;c++)
{
rxstat[i][c-0x20]=reg_read(port_offset+c);
}
port_offset = port_offset + 0x80;
}
eprintf("Reading tx stat registers -- \n");
for (i=0;i<=3;i++)
{
for (c=0x40;c<=0x58;c++)
{
txstat[i][c-0x40]=reg_read(port_offset+c);
}
port_offset = port_offset + 0x80;
}
spRestore();
check_error_display_rxstats();
check_error_display_txstats();
}
/** This function displays the messages for
respective error conditions only. **/
void check_error_display_rxstats(void)
{
short port = 0, rxport = 0;
for (port=0;port<=3;port++)
{
if ((channel == 'f') && (ports != 4))
{
rxport = ports;
}
if ((channel == 'c') && (ports != 4))
{
switch(ports)
{
case 0: rxport = 1;
break;
case 1: rxport = 0;
break;
case 2: rxport = 3;
break;
case 3: rxport = 2;
break;
}
}
if (ports == 4)
rxport = port;
if (port != rxport)
continue;
eprintf("\n Rx Statistics for port %d\n",rxport);
eprintf("-------------------------------\n");
eprintf("Rx Unicast packets : %d\n",rxstat[port][2]);
eprintf("Rx 64 byte packets : %d\n",rxstat[port][5]);
eprintf("Rx 65-127 byte packets : %d\n",rxstat[port][6]);
eprintf("Rx 128-255 byte packets : %d\n",rxstat[port][7]);
eprintf("Rx FCS Errors : %d\n",rxstat[port][12]);
eprintf("Rx Rx Data Errors : %d\n",rxstat[port][14]);
eprintf("Rx Align Errors : %d\n",rxstat[port][15]);
eprintf("Rx Jabber Errors : %d\n",rxstat[port][17]);
eprintf("Rx Runt Errors : %d\n",rxstat[port][21]);
eprintf("Rx Carrier Extend Errors : %d\n",rxstat[port][23]);
eprintf("Rx Sequence Errors : %d\n",rxstat[port][24]);
eprintf("Rx Symbol Errors : %d\n",rxstat[port][25]);
}
}
void check_error_display_txstats()
{
short port = 0, txport = 0;
for (port=0;port<=3;port++)
{
if (ports != 4)
{
txport = ports;
}
else
txport = port;
if (port != txport)
continue;
eprintf("\n Tx Statistics for port %d\n",txport);
eprintf("-------------------------------\n");
eprintf("Tx Unicast packets : %d\n",txstat[port][2]);
eprintf("Tx 64 byte packets : %d\n",txstat[port][5]);
eprintf("Tx 65-127 byte packets : %d\n",txstat[port][6]);
eprintf("Tx 128-255 byte packets : %d\n",txstat[port][7]);
eprintf("Tx FCS Errors : %d\n",txstat[port][12]);
eprintf("Tx Excessive collision Errors : %d\n",txstat[port][17]);
eprintf("Tx Excessive Deferral Errors : %d\n",txstat[port][18]);
eprintf("Tx Underrun : %d\n",txstat[port][20]);
eprintf("Tx CRC Errors : %d\n",txstat[port][22]);
}
}
void gets(char *str, int len)
{
char temp[30];
getCmdLine(temp);
memcpy(str, temp, (len - 1));
str[len - 1] = '\0';
}
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