📄 mac_init.c
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if(((!media_seat) && (!mdio_enabled)) || ((media_seat) && (!sf_mdio_enabled)))
{
reg_write(MDIO_CTL,0x6); // enable mdi and autoscan
s_ReadValue = reg_read((unsigned int)MDIO_CTL);
s_ReadValue = s_ReadValue >> 3;
s_ReadValue &= DEFAULT_SET;
mdio_done = s_ReadValue;
while(mdio_done != 0)
{
ctr++;
hal_delay_us(10000);
if (ctr > 5)
{
eprintf("ERROR: COULD NOT PERFORM MDIO READ\n");
return 0;
}
s_ReadValue = reg_read((unsigned int)MDIO_CTL);
s_ReadValue = s_ReadValue >> 3;
s_ReadValue &= DEFAULT_SET;
mdio_done = s_ReadValue;
}
ctr = 0;
if(media_seat)
{
sf_mdio_enabled = 1;
}
else
{
mdio_enabled = 1;
}
}
s_RegAddress = arg_RegAddress;
s_PhyAddress = phy << PHY_DEVICE_SHIFT;
s_WriteValue = s_PhyAddress | s_RegAddress;
s_WriteValue = s_WriteValue | PHY_READ;
reg_write(MDIO_SNGL_CMD, s_WriteValue); // write command to mdio
s_ReadValue = reg_read((unsigned int)MDIO_SNGL_CMD);
s_ReadValue = s_ReadValue >> 20;
s_ReadValue &= DEFAULT_SET;
mdio_done = s_ReadValue;
while(mdio_done != 0)
{
ctr++;
hal_delay_us(10000);
if (ctr > 5)
{
eprintf("ERROR: COULD NOT PERFORM MDIO READ\n");
break;
}
s_ReadValue = reg_read((unsigned int)MDIO_SNGL_CMD);
s_ReadValue = s_ReadValue >> 20;
s_ReadValue &= DEFAULT_SET;
mdio_done = s_ReadValue;
}
if(ctr < 6)
return(reg_read(MDIO_SINGLE_RW_DATA) >> 16);
else
return 0;
}
void mac_config(void)
{
int port=0;
for(port=0; port<NUM_PORTS;port++)
{
reg_write((PKT_FILTER_CTL+(port*PORTSZ)),0);
}
}
void fiber_init()
{
/* apply reset to MAC device */
mac_reset_config();
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(SERDES_CLKMODE_REG,0xf);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(PORT_ENABLE,0x0);
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(INTERFACE_MODE,0x0); /** enable fiber mode **/
reg_write(SERDES_CLKMODE_REG,0xF);
reg_write(SPI3_TX_GLOBAL_CONFIG,0x20aa0f);
reg_write(SPI3_RX_CONFIG, 0xAA0F80);
reg_write(LED_MODE, 0x3);
/* enable crc addition */
reg_write(DIV_CONFIG_WORD,0x116D);
reg_write(DIV_CONFIG_WORD+INDEX_PORT1,0x116D);
reg_write(DIV_CONFIG_WORD+INDEX_PORT2,0x116D);
reg_write(DIV_CONFIG_WORD+INDEX_PORT3,0x116D);
/* enable crc strip */
reg_write(0x5B3,0xF0);
/* Pause control not to be disabled */
/*
reg_write(FC_MODE,0);
reg_write(FC_MODE+INDEX_PORT1,0);
reg_write(FC_MODE+INDEX_PORT2,0);
reg_write(FC_MODE+INDEX_PORT3,0);
*/
reg_write(TXFIFO_PAD_ENB,0xAAAA);
reg_write(SERDES_TX_RX_POW_DOWN,0x0);
reg_write((RXFIFO_DROP_ENABLE),0x0);
mac_config();
mac_disable_reset();
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(SERDES_CLKMODE_REG,0xf);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(PORT_ENABLE,0xF);
}
#if 0
void gig_config()
{
short s_PortCount=0;
for(s_PortCount=0; s_PortCount<4;s_PortCount++)
{
gbe_mac_phy_write(s_PortCount, 31, 0x0);
gbe_mac_phy_write(s_PortCount, 27, 0x15);
gbe_mac_phy_write(s_PortCount, 31, 0x0);
gbe_mac_phy_write(s_PortCount, 9, 0x1b00);
gbe_mac_phy_write(s_PortCount, 31, 0x2a30);
gbe_mac_phy_write(s_PortCount, 8, 0x208);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xa242);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 0, 0x8242);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xa244);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x298d);
gbe_mac_phy_write(s_PortCount, 0, 0x8244);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xa244);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x289a);
gbe_mac_phy_write(s_PortCount, 0, 0x8244);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xa246);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x3fb1);
gbe_mac_phy_write(s_PortCount, 0, 0x8246);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xa246);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x3fc0);
gbe_mac_phy_write(s_PortCount, 0, 0x8246);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xaa42);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x218d);
gbe_mac_phy_write(s_PortCount, 0, 0x8a42);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xaa42);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 0, 0x8a42);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xaa44);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x298d);
gbe_mac_phy_write(s_PortCount, 0, 0x8a44);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xaa44);
gbe_mac_phy_write(s_PortCount, 1, 0x289a);
gbe_mac_phy_write(s_PortCount, 0, 0x8a44);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xaa46);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x3fb1);
gbe_mac_phy_write(s_PortCount, 0, 0x8a46);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 31, 0xaa46);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x3fc0);
gbe_mac_phy_write(s_PortCount, 31, 0x8a46);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xb242);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x218d);
gbe_mac_phy_write(s_PortCount, 0, 0x9242);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xb242);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x2066);
gbe_mac_phy_write(s_PortCount, 0, 0x9242);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xb242);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x2066);
gbe_mac_phy_write(s_PortCount, 0, 0x9242);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xb244);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x298d);
gbe_mac_phy_write(s_PortCount, 0, 0x9244);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xb244);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x289a);
gbe_mac_phy_write(s_PortCount, 0, 0x9244);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xb246);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x3fb1);
gbe_mac_phy_write(s_PortCount, 0, 0x9246);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xb246);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x3fc0);
gbe_mac_phy_write(s_PortCount, 0, 0x9246);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xba42);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x218d);
gbe_mac_phy_write(s_PortCount, 0, 0x9a42);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xba42);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x2066);
gbe_mac_phy_write(s_PortCount, 0, 0x9a42);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xba44);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x298d);
gbe_mac_phy_write(s_PortCount, 0, 0x9a44);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xba44);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x289a);
gbe_mac_phy_write(s_PortCount, 0, 0x9a44);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xba46);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x3fb1);
gbe_mac_phy_write(s_PortCount, 0, 0x9a46);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xba46);
gbe_mac_phy_write(s_PortCount, 2, 0x0);
gbe_mac_phy_write(s_PortCount, 1, 0x3fc0);
gbe_mac_phy_write(s_PortCount, 0, 0x9a46);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xa70c);
gbe_mac_phy_write(s_PortCount, 2, 0xf0);
gbe_mac_phy_write(s_PortCount, 1, 0xe30d);
gbe_mac_phy_write(s_PortCount, 0, 0x870c);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xa770);
gbe_mac_phy_write(s_PortCount, 2, 0x85);
gbe_mac_phy_write(s_PortCount, 1, 0x1ff0);
gbe_mac_phy_write(s_PortCount, 0, 0x8770);
gbe_mac_phy_write(s_PortCount, 31, 0x52b5);
gbe_mac_phy_write(s_PortCount, 0, 0xa770);
gbe_mac_phy_write(s_PortCount, 2, 0x85);
gbe_mac_phy_write(s_PortCount, 1, 0x1f40);
gbe_mac_phy_write(s_PortCount, 0, 0x8770);
gbe_mac_phy_write(s_PortCount, 31, 0x2a30);
gbe_mac_phy_write(s_PortCount, 8, 0x8);
gbe_mac_phy_write(s_PortCount, 31, 0x2a30);
gbe_mac_phy_write(s_PortCount, 5, 0x8018);
gbe_mac_phy_write(s_PortCount, 31, 0x0);
gbe_mac_phy_write(s_PortCount, 24, 0x2247);
gbe_mac_phy_write(s_PortCount, 31, 0x0);
gbe_mac_phy_write(s_PortCount, 0, 0x140);
}
}
#endif
void ShowRegisterVal(void)
{
spConfig();
eprintf(" Vallejo Register configuration -- \n");
eprintf("JTAG id : 0x%x\n",reg_read(0x50C));
eprintf("Port Enable : 0x%x\n",reg_read(0x500));
eprintf("Loopback : 0x%x\n",reg_read(0x5b2));
eprintf("Mini frame padding : 0x%x\n",reg_read(0x63E));
eprintf("Interface mode : 0x%x\n",reg_read(0x501));
eprintf("Diverse Config : 0x%x\n",reg_read(0x018));
eprintf("Desired Duplex : 0x%x\n",reg_read(0x02));
eprintf("Rx Config word : 0x%x\n",reg_read(0x16));
eprintf("SPI-3 Tx : 0x%x\n",reg_read(0x700));
eprintf("SPI-3 Rx : 0x%x\n",reg_read(0x701));
eprintf("LED control : 0x%x\n",reg_read(0x509));
eprintf("Station Address Low: 0x%x\n",reg_read(0x0));
eprintf("Station Address High: 0x%x\n",reg_read(0x1));
eprintf("PORT0_RX_HIGH_WATERMARK:0x%x\n",reg_read(PORT0_RX_HIGH_WATERMARK));
eprintf("PORT1_RX_HIGH_WATERMARK:0x%x\n",reg_read(PORT1_RX_HIGH_WATERMARK));
eprintf("PORT2_RX_HIGH_WATERMARK:0x%x\n",reg_read(PORT2_RX_HIGH_WATERMARK));
eprintf("PORT3_RX_HIGH_WATERMARK:0x%x\n",reg_read(PORT3_RX_HIGH_WATERMARK));
eprintf("PORT0_RX_LOW_WATERMARK:0x%x\n",reg_read(PORT0_RX_LOW_WATERMARK));
eprintf("PORT1_RX_LOW_WATERMARK:0x%x\n",reg_read(PORT1_RX_LOW_WATERMARK));
eprintf("PORT2_RX_LOW_WATERMARK:0x%x\n",reg_read(PORT2_RX_LOW_WATERMARK));
eprintf("PORT3_RX_LOW_WATERMARK:0x%x\n",reg_read(PORT3_RX_LOW_WATERMARK));
eprintf("RXFIFO_DROP_ENABLE: 0x%x\n",reg_read(RXFIFO_DROP_ENABLE));
eprintf("RXFIFO_CAPT_LPBK_ENB: 0x%x\n",reg_read(RXFIFO_CAPT_LPBK_ENB));
eprintf("RXFIFO_PAD_CRCSTRIP_ENB: 0x%x\n",reg_read(RXFIFO_PAD_CRCSTRIP_ENB));
eprintf("PORT0_TX_HIGH_WATERMARK:0x%x\n",reg_read(PORT0_TX_HIGH_WATERMARK));
eprintf("PORT1_TX_HIGH_WATERMARK:0x%x\n",reg_read(PORT1_TX_HIGH_WATERMARK));
eprintf("PORT2_TX_HIGH_WATERMARK:0x%x\n",reg_read(PORT2_TX_HIGH_WATERMARK));
eprintf("PORT3_TX_HIGH_WATERMARK:0x%x\n",reg_read(PORT3_TX_HIGH_WATERMARK));
eprintf("PORT0_TX_LOW_WATERMARK:0x%x\n",reg_read(PORT0_TX_LOW_WATERMARK));
eprintf("PORT1_TX_LOW_WATERMARK:0x%x\n",reg_read(PORT1_TX_LOW_WATERMARK));
eprintf("PORT2_TX_LOW_WATERMARK:0x%x\n",reg_read(PORT2_TX_LOW_WATERMARK));
eprintf("PORT3_TX_LOW_WATERMARK:0x%x\n",reg_read(PORT3_TX_LOW_WATERMARK));
eprintf("PORT0_TX_MAC_THRESHOLD: 0x%x\n",reg_read(PORT0_TX_MAC_THRESHOLD));
eprintf("PORT1_TX_MAC_THRESHOLD: 0x%x\n",reg_read(PORT1_TX_MAC_THRESHOLD));
eprintf("PORT2_TX_MAC_THRESHOLD: 0x%x\n",reg_read(PORT2_TX_MAC_THRESHOLD));
eprintf("PORT3_TX_MAC_THRESHOLD: 0x%x\n",reg_read(PORT3_TX_MAC_THRESHOLD));
eprintf("TXFIFO_OVFLW: 0x%x\n",reg_read(TXFIFO_OVFLW));
eprintf("LOOP_RXDATA_TXFIFO: 0x%x\n",reg_read(LOOP_RXDATA_TXFIFO));
eprintf("PORT0_TX_FRAME_REMOVED: 0x%x\n",reg_read(PORT0_TX_FRAME_REMOVED));
eprintf("PORT1_TX_FRAME_REMOVED: 0x%x\n",reg_read(PORT0_TX_FRAME_REMOVED));
eprintf("PORT2_TX_FRAME_REMOVED: 0x%x\n",reg_read(PORT0_TX_FRAME_REMOVED));
eprintf("PORT3_TX_FRAME_REMOVED: 0x%x\n",reg_read(PORT0_TX_FRAME_REMOVED));
spRestore();
}
void mixed_mode_init(UINT32 set_int_lpbk)
{
// if(!set_int_lpbk)
// {
// config_phy();
// }
// else
// {
// config_phy_for_line_lpbk();
// }
// apply reset to MAC device
config_phy();
mac_reset_config();
reg_write(PORT_ENABLE,0x0);
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(SERDES_CLKMODE_REG,0xf);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(PORT_ENABLE,0x0);
reg_write(SERDES_CLKMODE_REG,0x0);
if (cport == 0)
{
reg_write(INTERFACE_MODE,0x3); // enable copper mode on port 0 and 1
}
else
{
reg_write(INTERFACE_MODE,0xC); // enable copper mode on port 2 and 3
}
// switch(dplx)
// {
// /* chinmay: only Cu ports can be in half duplex mode */
// case 'h' : reg_write(DESIRED_DUPLEX,0x0);
// reg_write(DESIRED_DUPLEX+INDEX_PORT1,0x0);
// //reg_write(DESIRED_DUPLEX+INDEX_PORT2,0x0);
// //reg_write(DESIRED_DUPLEX+INDEX_PORT3,0x0);
// break;
// case 'f' :
if (cport == 0)
{
reg_write(DESIRED_DUPLEX,0x1);
reg_write(DESIRED_DUPLEX+INDEX_PORT1,0x1);
}
else
{
reg_write(DESIRED_DUPLEX+INDEX_PORT2,0x1);
reg_write(DESIRED_DUPLEX+INDEX_PORT3,0x1);
}
// break;
// default : eprintf("Illegal duplex optinon.\n");
// eprintf("The opertation will be full duplex..\n");
// break;
// }
//For mixed mode, fiber ports must always be in full duplex
// reg_write(DESIRED_DUPLEX+INDEX_PORT2,0x1);
// reg_write(DESIRED_DUPLEX+INDEX_PORT3,0x1);
reg_write(SERDES_CLKMODE_REG,0xF);
//#ifdef SPHY4x8
reg_write(SPI3_TX_GLOBAL_CONFIG,0x20aa0f);
//#else
// reg_write(SPI3_TX_GLOBAL_CONFIG,0x00aa0f);
//#endif
// Enable CRC addition
if (cport == 0)
{
reg_write(DIV_CONFIG_WORD,0x114D); // Cu
reg_write(DIV_CONFIG_WORD+INDEX_PORT1,0x114D); // Cu
reg_write(DIV_CONFIG_WORD+INDEX_PORT2,0x116D); // Fibre
reg_write(DIV_CONFIG_WORD+INDEX_PORT3,0x116D); // Fibre
}
else
{
reg_write(DIV_CONFIG_WORD,0x116D); // Fibre
reg_write(DIV_CONFIG_WORD+INDEX_PORT1,0x116D); // Fibre
reg_write(DIV_CONFIG_WORD+INDEX_PORT2,0x114D); // Cu
reg_write(DIV_CONFIG_WORD+INDEX_PORT3,0x114D); // Cu
}
// Enable CRC stripping
reg_write(0x5B3,0xF0);
reg_write(SERDES_CLKMODE_REG,0x0);
// if (speed == 100)
// {
// reg_write(MAC_IF_MODE,0x5);
// reg_write(MAC_IF_MODE+INDEX_PORT1,0x5);
// //reg_write(MAC_IF_MODE+INDEX_PORT2,0x5);
// //reg_write(MAC_IF_MODE+INDEX_PORT3,0x5);
// }
// if (speed == 10)
// {
// reg_write(MAC_IF_MODE,0x4);
// reg_write(MAC_IF_MODE+INDEX_PORT1,0x4);
// //reg_write(MAC_IF_MODE+INDEX_PORT2,0x4);
// //reg_write(MAC_IF_MODE+INDEX_PORT3,0x4);
// }
//
// if (speed == 1000)
// {
if (cport == 0)
{
reg_write(MAC_IF_MODE,0x6);
reg_write(MAC_IF_MODE+INDEX_PORT1,0x6);
}
else
{
reg_write(MAC_IF_MODE+INDEX_PORT2,0x6);
reg_write(MAC_IF_MODE+INDEX_PORT3,0x6);
}
// //reg_write(MAC_IF_MODE+INDEX_PORT2,0x6);
// //reg_write(MAC_IF_MODE+INDEX_PORT3,0x6);
// }
reg_write(SERDES_CLKMODE_REG,0xF);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(TXFIFO_PAD_ENB,0xAAAA);
reg_write(GBIC_CTRL_REG,0x1C00);
reg_write(LED_MODE, 0x3);
// Activate units
reg_write(0x505, 0x0); // MAC Soft reset
reg_write(0x506, 0x0); // MDIO Reset
reg_write(0x620, 0x0); // TX FIFO Reset
reg_write(0x59E, 0x0); // Rx FIFO Reset
mac_disable_reset();
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(SERDES_CLKMODE_REG,0xf);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(PORT_ENABLE,0xF);
}
void mixed_mode_init1(UINT32 set_int_lpbk)
{
if(!set_int_lpbk)
{
config_phy();
}
else
{
config_phy_for_line_lpbk();
}
/* apply reset to MAC device */
mac_reset_config();
reg_write(PORT_ENABLE,0x0);
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(SERDES_CLKMODE_REG,0xf);
reg_write(0x505,0xf);
reg_write(0x505,0x0);
reg_write(PORT_ENABLE,0x0);
reg_write(SERDES_CLKMODE_REG,0x0);
reg_write(INTERFACE_MODE,0x3); // enable copper mode on port 0 and 1
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