📄 register_map.h
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/*
*-------------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
* ------------------------------------------------------------------------------
*/
#if !defined(__REG_MAP_H__)
#define __REG_MAP_H__
#if defined(__cplusplus)
extern "C"
{
#endif /* end defined(__cplusplus) */
/**
* Pre-processor symbol and macro definitions.
*
*/
#define NUM_PORTS 0x4
// per port index
#define INDEX_PORT0 0x00
#define INDEX_PORT1 0x80
#define INDEX_PORT2 0x100
#define INDEX_PORT3 0x180
// per port control register offsets
#define STATION_ADDR_LOW 0x00
#define STATION_ADDR_HIGH 0x01
#define DESIRED_DUPLEX 0x02
#define FDFC_TYPE 0x03
#define VLAN_TYPE 0x04
#define COLL_DIST 0x05
#define COLL_TSHD 0x06
#define FCTX_TIMER 0x07
#define FDFC_ADDR_LOW 0x08
#define FDFC_ADDR_HIGH 0x09
#define IPG_RECEIVE_TIME1 0x0A
#define IPG_RECEIVE_TIME2 0x0B
#define IPG_TRANSMIT_TIME 0x0C
#define PAUSE_THRESHOLD 0x0E
#define MAX_FRAME_SIZE 0x0F
#define MAC_IF_MODE 0x10
#define FLUSH_TX 0x11
#define FC_MODE 0x12
#define FC_BACK_PRESSURE_LEN 0x13
#define SHORT_RUNT_TSHD 0x14
#define UNKNOWN_FRAME_STT 0x15
#define RX_CONFIG_WORD 0x16
#define TX_CONFIG_WORD 0x17
#define DIV_CONFIG_WORD 0x18
#define PKT_FILTER_CTL 0x19
#define MUL_PORT_ADDR_LOW 0x1A
#define MUL_PORT_ADDR_HIGH 0x1B
//per port stat register offsets
#define RX_OCTETS_OK 0x20
#define RX_OCTETS_BAD 0x21
#define RX_UC_PKTS 0x22
#define RX_MC_PKTS 0x23
#define RX_BC_PKTS 0x24
#define RX_PKTS_64 0x25
#define RX_PKTS_65_127 0x26
#define RX_PKTS_128_255 0x27
#define RX_PKTS_256_511 0x28
#define RX_PKTS_512_1023 0x29
#define RX_PKTS_1024_1518 0x2A
#define RX_PKTS_1519_MAX 0x2B
#define RX_FCS_ERR 0x2C
#define VLAN_TAG 0x2D
#define RX_DATA_ERR 0x2E
#define RX_ALIGN_ERR 0x2F
#define RX_LONG_ERR 0x30
#define RX_JABBER_ERR 0x31
#define RX_PAUSE_MAC_CTL 0x32
#define RX_UNKNOWN_CTL_FRAME 0x33
#define VLONG_ERR 0x34
#define RUNT_ERR 0x35
#define SHORT_ERR 0x36
#define SEQ_ERR 0x38
#define SYMBOL_ERR 0x39
//per port TX statistics register offsets
#define TX_OCTETS_OK 0x40
#define TX_OCTETS_BAD 0x41
#define TX_UC_PKTS 0x42
#define TX_MC_PKTS 0x43
#define TX_BC_PKTS 0x44
#define TX_PKTS_64 0x45
#define TX_PKTS_65_127 0x46
#define TX_PKTS_128_255 0x47
#define TX_PKTS_256_511 0x48
#define TX_PKTS_512_1023 0x49
#define TX_PKTS_1024_1518 0x4A
#define TX_PKTS_1519_MAX 0x4B
#define TX_DEFERRED_ERR 0x4C
#define TX_TOTAL_COLLISION 0x4D
#define TX_SINGLE_COLLISION 0x4E
#define TX_MUL_COLLISION 0x4F
#define LATE_COLLISION 0x50
#define TX_EXCV_COLLISION 0x51
#define TX_EXCV_DEFERRED_ERR 0x52
#define TX_EXCV_LEN_DROP 0x53
#define TX_UNDERRUN 0x54
#define TX_VLAN_TAG 0x55
#define TX_CRC_ERR 0x56
#define TX_PAUSE_FRAME 0x57
#define FC_COLLISION_SEND 0x58
//PHY autoscan register offsets
#define AS_CTL_REG 0x60
#define AS_STAT 0x61
#define AS_PHY_ID_REG1 0x62
#define AS_PHY_ID_REG2 0x63
#define AN_ADVT_REG 0x64
#define AN_LP_BSPG_ABL 0x65
#define AN_EXP_REG 0x66
#define AN_NXTPG_TX 0x67
// global status and configuration register offsets
#define TOP_CONFIG_BASE 0x500
#define PORT_ENABLE TOP_CONFIG_BASE + 0x00
#define INTERFACE_MODE TOP_CONFIG_BASE + 0x01
#define LINK_UP_STATUS TOP_CONFIG_BASE + 0x02
#define PHY_REF_CLK_SEL TOP_CONFIG_BASE + 0x03
#define RESET_CORE_CLOCK TOP_CONFIG_BASE + 0x04
#define MAC_SOFT_RESET TOP_CONFIG_BASE + 0x05
#define MDIO_RESET TOP_CONFIG_BASE + 0x06
#define PAUSE_BEHAVIOR TOP_CONFIG_BASE + 0x07
#define UI_ENDIAN_MODE TOP_CONFIG_BASE + 0x08
#define LED_MODE TOP_CONFIG_BASE + 0x09
#define LED_FLASH_RATE TOP_CONFIG_BASE + 0x0A
#define LED_FAULT_ACTION TOP_CONFIG_BASE + 0x0B
#define JTAG_ID TOP_CONFIG_BASE + 0x0C
// Rx FIFO Register offset
#define RX_FIFO_BASE 0x580
#define PORT0_RX_HIGH_WATERMARK RX_FIFO_BASE + 0x00
#define PORT1_RX_HIGH_WATERMARK RX_FIFO_BASE + 0x01
#define PORT2_RX_HIGH_WATERMARK RX_FIFO_BASE + 0x02
#define PORT3_RX_HIGH_WATERMARK RX_FIFO_BASE + 0x03
#define PORT0_RX_LOW_WATERMARK RX_FIFO_BASE + 0x0A
#define PORT1_RX_LOW_WATERMARK RX_FIFO_BASE + 0x0B
#define PORT2_RX_LOW_WATERMARK RX_FIFO_BASE + 0x0C
#define PORT3_RX_LOW_WATERMARK RX_FIFO_BASE + 0x0D
#define PORT0_RX_FRAME_REMOVED RX_FIFO_BASE + 0x14
#define PORT1_RX_FRAME_REMOVED RX_FIFO_BASE + 0x15
#define PORT2_RX_FRAME_REMOVED RX_FIFO_BASE + 0x16
#define PORT3_RX_FRAME_REMOVED RX_FIFO_BASE + 0x17
#define RXFIFO_PORT_RESET RX_FIFO_BASE + 0x1E
#define RXFIFO_DROP_ENABLE RX_FIFO_BASE + 0x1F
#define RXFIFO_OVRFLW_EVENT RX_FIFO_BASE + 0x20
#define RXFIFO_OUT_OF_SEQ RX_FIFO_BASE + 0x21
#define PORT0_RXFIFO_PKT_DROP RX_FIFO_BASE + 0x22
#define PORT1_RXFIFO_PKT_DROP RX_FIFO_BASE + 0x23
#define PORT2_RXFIFO_PKT_DROP RX_FIFO_BASE + 0x24
#define PORT3_RXFIFO_PKT_DROP RX_FIFO_BASE + 0x25
#define PORT0_RXFIFO_RW_PTR RX_FIFO_BASE + 0x26
#define PORT1_RXFIFO_RW_PTR RX_FIFO_BASE + 0x27
#define PORT2_RXFIFO_RW_PTR RX_FIFO_BASE + 0x28
#define PORT3_RXFIFO_RW_PTR RX_FIFO_BASE + 0x29
#define RXPORT0_OCCUPNCY_CTR RX_FIFO_BASE + 0x2A
#define RXPORT1_OCCUPNCY_CTR RX_FIFO_BASE + 0x2B
#define RXPORT2_OCCUPNCY_CTR RX_FIFO_BASE + 0x2C
#define RXPORT3_OCCUPNCY_CTR RX_FIFO_BASE + 0x2D
#define CAPTURED_PKT_LEN RX_FIFO_BASE + 0x2E
#define INDIRECT_ACC_CTL RX_FIFO_BASE + 0x2F
#define INDIRECT_MEM_DATA_REG1 RX_FIFO_BASE + 0x30
#define INDIRECT_MEM_DATA_REG2 RX_FIFO_BASE + 0x31
#define RXFIFO_CAPT_LPBK_ENB RX_FIFO_BASE + 0x32
#define RXFIFO_PAD_CRCSTRIP_ENB RX_FIFO_BASE + 0x33
#define PORT0_MATCH_PATTERN RX_FIFO_BASE + 0x34
#define PORT1_MATCH_PATTERN RX_FIFO_BASE + 0x35
#define PORT2_MATCH_PATTERN RX_FIFO_BASE + 0x36
#define PORT3_MATCH_PATTERN RX_FIFO_BASE + 0x37
#define PORT0_JUMBO_PKT_SIZE RX_FIFO_BASE + 0x38
#define PORT1_JUMBO_PKT_SIZE RX_FIFO_BASE + 0x39
#define PORT2_JUMBO_PKT_SIZE RX_FIFO_BASE + 0x3A
#define PORT3_JUMBO_PKT_SIZE RX_FIFO_BASE + 0x3B
#define PKT_DROP_CAP_FIFO_0 RX_FIFO_BASE + 0x3C
#define PKT_DROP_CAP_FIFO_1 RX_FIFO_BASE + 0x3D
#define PKT_DROP_CAP_FIFO_2 RX_FIFO_BASE + 0x3E
#define PKT_DROP_CAP_FIFO_3 RX_FIFO_BASE + 0x3F
// Tx FIFO Register offset
#define TX_FIFO_BASE 0x600
#define PORT0_TX_HIGH_WATERMARK TX_FIFO_BASE + 0x00
#define PORT1_TX_HIGH_WATERMARK TX_FIFO_BASE + 0x01
#define PORT2_TX_HIGH_WATERMARK TX_FIFO_BASE + 0x02
#define PORT3_TX_HIGH_WATERMARK TX_FIFO_BASE + 0x03
#define PORT0_TX_LOW_WATERMARK TX_FIFO_BASE + 0x0A
#define PORT1_TX_LOW_WATERMARK TX_FIFO_BASE + 0x0B
#define PORT2_TX_LOW_WATERMARK TX_FIFO_BASE + 0x0C
#define PORT3_TX_LOW_WATERMARK TX_FIFO_BASE + 0x0D
#define PORT0_TX_MAC_THRESHOLD TX_FIFO_BASE + 0x14
#define PORT1_TX_MAC_THRESHOLD TX_FIFO_BASE + 0x15
#define PORT2_TX_MAC_THRESHOLD TX_FIFO_BASE + 0x16
#define PORT3_TX_MAC_THRESHOLD TX_FIFO_BASE + 0x17
#define TXFIFO_OVFLW TX_FIFO_BASE + 0x1E
#define LOOP_RXDATA_TXFIFO TX_FIFO_BASE + 0x1F
#define TXFIFO_PORT_RESET TX_FIFO_BASE + 0x20
#define PORT0_TX_FRAME_REMOVED TX_FIFO_BASE + 0x21
#define PORT1_TX_FRAME_REMOVED TX_FIFO_BASE + 0x22
#define PORT2_TX_FRAME_REMOVED TX_FIFO_BASE + 0x23
#define PORT3_TX_FRAME_REMOVED TX_FIFO_BASE + 0x24
#define PORT0_TXFIFO_PKT_DROP TX_FIFO_BASE + 0x25
#define PORT1_TXFIFO_PKT_DROP TX_FIFO_BASE + 0x26
#define PORT2_TXFIFO_PKT_DROP TX_FIFO_BASE + 0x27
#define PORT3_TXFIFO_PKT_DROP TX_FIFO_BASE + 0x28
#define PORT0_TXFIFO_RW_PTR TX_FIFO_BASE + 0x29
#define PORT1_TXFIFO_RW_PTR TX_FIFO_BASE + 0x2A
#define PORT2_TXFIFO_RW_PTR TX_FIFO_BASE + 0x2B
#define PORT3_TXFIFO_RW_PTR TX_FIFO_BASE + 0x2C
#define TXPORT0_OCCUPNCY_CTR TX_FIFO_BASE + 0x2D
#define TXPORT1_OCCUPNCY_CTR TX_FIFO_BASE + 0x2E
#define TXPORT2_OCCUPNCY_CTR TX_FIFO_BASE + 0x2F
#define TXPORT3_OCCUPNCY_CTR TX_FIFO_BASE + 0x30
#define PORT0_INS_FIFO_DATA_REG0 TX_FIFO_BASE + 0x31
#define PORT0_INS_FIFO_DATA_REG1 TX_FIFO_BASE + 0x32
#define PORT0_INS_FIFO_CTL_REG TX_FIFO_BASE + 0x33
#define PORT1_INS_FIFO_DATA_REG0 TX_FIFO_BASE + 0x34
#define PORT1_INS_FIFO_DATA_REG1 TX_FIFO_BASE + 0x35
#define PORT1_INS_FIFO_CTL_REG TX_FIFO_BASE + 0x36
#define PORT2_INS_FIFO_DATA_REG0 TX_FIFO_BASE + 0x37
#define PORT2_INS_FIFO_DATA_REG1 TX_FIFO_BASE + 0x38
#define PORT2_INS_FIFO_CTL_REG TX_FIFO_BASE + 0x39
#define PORT3_INS_FIFO_DATA_REG0 TX_FIFO_BASE + 0x3A
#define PORT3_INS_FIFO_DATA_REG1 TX_FIFO_BASE + 0x3B
#define PORT3_INS_FIFO_CTL_REG TX_FIFO_BASE + 0x3C
#define TXFIFO_PORTDROP_INS_ENB TX_FIFO_BASE + 0x3D
#define TXFIFO_PAD_ENB TX_FIFO_BASE + 0x3E
// MDIO Register offsets
#define MDIO_BASE 0x680
#define MDIO_SNGL_CMD MDIO_BASE + 0x00
#define MDIO_SINGLE_RW_DATA MDIO_BASE + 0x01
#define AS_PHY_ADDR MDIO_BASE + 0x02
#define MDIO_CTL MDIO_BASE + 0x03
//SPI-3 register offsets
#define SPI3_BASE 0x700
#define SPI3_TX_GLOBAL_CONFIG SPI3_BASE + 0x00
#define SPI3_RX_CONFIG SPI3_BASE + 0x01
#define SPI3_TX_INT_STATUS_PORT0 SPI3_BASE + 0x02 + INDEX_PORT0
#define SPI3_TX_INT_STATUS_PORT1 SPI3_BASE + 0x02 + INDEX_PORT1
#define SPI3_TX_INT_STATUS_PORT2 SPI3_BASE + 0x02 + INDEX_PORT2
#define SPI3_TX_INT_STATUS_PORT3 SPI3_BASE + 0x02 + INDEX_PORT3
#define SPI3_ADR_PARITY_ERROR_PORT0 SPI3_BASE + 0x0A + INDEX_PORT0
#define SPI3_ADR_PARITY_ERROR_PORT1 SPI3_BASE + 0x0A + INDEX_PORT1
#define SPI3_ADR_PARITY_ERROR_PORT2 SPI3_BASE + 0x0A + INDEX_PORT2
#define SPI3_ADR_PARITY_ERROR_PORT3 SPI3_BASE + 0x0A + INDEX_PORT3
#define SPI3_PKT_DROP_CTR_PORT0 SPI3_BASE + 0x0B
#define SPI3_SYNCERR_DROP_CTR_PORT0 SPI3_BASE + 0x0C
#define SPI3_PKT_SHORT_DROP_CTR_PORT0 SPI3_BASE + 0x0D
#define SPI3_PKT_DROP_CTR_PORT1 SPI3_BASE + 0x0E
#define SPI3_SYNCERR_DROP_CTR_PORT1 SPI3_BASE + 0x0F
#define SPI3_PKT_SHORT_DROP_CTR_PORT1 SPI3_BASE + 0x10
#define SPI3_PKT_DROP_CTR_PORT2 SPI3_BASE + 0x11
#define SPI3_SYNCERR_DROP_CTR_PORT2 SPI3_BASE + 0x12
#define SPI3_PKT_SHORT_DROP_CTR_PORT2 SPI3_BASE + 0x13
#define SPI3_PKT_DROP_CTR_PORT3 SPI3_BASE + 0x14
#define SPI3_SYNCERR_DROP_CTR_PORT3 SPI3_BASE + 0x15
#define SPI3_PKT_SHORT_DROP_CTR_PORT3 SPI3_BASE + 0x16
//serdes register offset
#define SERDES_BASE 0x780
#define SERDES_ACDC_COUPLING SERDES_BASE + 0x00
#define SERDES_TX_LINK_VALIDATION SERDES_BASE + 0x06
#define SERDES_TX_RX_POW_DOWN SERDES_BASE + 0x07
#define SERDES_RX_DATA_SYNC SERDES_BASE + 0x08
#define SERDES_RX_LINK_VALIDATION SERDES_BASE + 0x09
#define SERDES_RX_LINK_STT SERDES_BASE + 0x0A
#define SERDES_RX_PHASE_ROT SERDES_BASE + 0x0B
#define SERDES_RX_PHASE_ROT_BUS SERDES_BASE + 0x0C
#define SERDES_RX_LATCH_OBSRV_01 SERDES_BASE + 0x0E
#define SERDES_RX_LATCH_OBSRV_23 SERDES_BASE + 0x0F
#define SERDES_RX_SIGNAL_LEVEL SERDES_BASE + 0x13
#define SERDES_CLKMODE_REG SERDES_BASE + 0x14
#define SERDES_RX_TEST_CTRL_REG SERDES_BASE + 0x15
#define SERDES_SERDES_TX_CONFIG SERDES_BASE + 0x16
#define SERDES_SERDES_RX_CONFIG SERDES_BASE + 0x17
#define SERDES_PLL_LOCK_STATUS SERDES_BASE + 0x18
#define GBIC_STATUS_REG SERDES_BASE + 0x19
#define GBIC_CTRL_REG SERDES_BASE + 0x1A
#define I2C_CTRL_REG SERDES_BASE + 0x1B
#define PLL1_TUNE_REG SERDES_BASE + 0x1C
#define PLL2_TUNE_REG SERDES_BASE + 0x1D
#define PLL3_TUNE_REG SERDES_BASE + 0x1E
/**
* Type definitions.
*/
/**
* Prototypes for interface functions.
*/
/**
* Exported variables.
*/
#if defined(__cplusplus)
}
#endif /* end defined(__cplusplus) */
#endif /* end !defined(__REG_MAP_H__) */
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