ixf6048.c

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

        WRITE_TO_HW(pReg, RegVal);
        /* PSN_END B1 RElease Changes*/
    }
    if( (Side == ixf6048_eSIDE_TRANSMIT) ||
        (Side == ixf6048_eSIDE_BOTH    ) )
    {  /* Tx Side Channel mode */
        /* PSN_ADDED for B1 Release  -- NOTE: RegVal Changes*/
        pReg = BaseAddress + ixf6048_T_COCNF_CHAN_OFFSET(iChanNum);
        RegVal = READ_FROM_HW(pReg);
        Ixf6048ClrBitVal(RegVal,ixf6048_mCHAN_MODE); /* Clear ChanMode bits */
        Ixf6048SetBitVal(RegVal, (pCfg->ChanMode & ixf6048_mCHAN_MODE));
        if(pCfg->TrScrEn == ixf6048_eTR_SCR_EN_SCRAMBLER_ENABLED)
            Ixf6048SetBitVal(RegVal, ixf6048_bXMT_TRANS_SCR_EN);
        else
            Ixf6048ClrBitVal(RegVal, ixf6048_bXMT_TRANS_SCR_EN);

        WRITE_TO_HW(pReg, RegVal);
        /* PSN_END B1 Release Changes*/
    }
    /* If In repeater mode, then the payload is passed directly, so 
    the configuration is ignored (below) */
    if(pCfg->RepeaterMode == ixf6048_eCHANNEL_IN_REPEATER_MODE)
        Ixf6048SetBit((BaseAddress + ixf6048_COCNF_CHAN_OFFSET(iChanNum)),
            ixf6048_bCHAN_REPEATER_MODE);
    else /* Must be in Normal Mode */
        Ixf6048ClrBit((BaseAddress + ixf6048_COCNF_CHAN_OFFSET(iChanNum)),
            ixf6048_bCHAN_REPEATER_MODE);

    /* Init the Channel Interface Configuration */
    if (pCfg->pChanIfCfg)
        rc = EditChanIfCfg( BaseAddress, iChanNum,Side, 
            pCfg->ChanMode, pCfg->pChanIfCfg);
    else
    {
        return bb_INV_CHAN_IF_CFG_USED;
    }

    /* Edit the OHT for each Channel */
    if (pCfg->pOhtChanCfg)
        rc = EditOhtChanCfg(BaseAddress, iChanNum, Side, pCfg->pOhtChanCfg);
    else
    {
        return bb_INV_SONET_SDH_CHAN_CFG_USED;
    }
    /* Configure the ATM or POS section if Used and NOT in Repeater Mode */
    if( (pCfg->RepeaterMode != ixf6048_eCHANNEL_IN_REPEATER_MODE ) &&
        (pCfg->ChanMode == ixf6048_eATM_MODE_CHAN) )
    {
        if (pCfg->pAtmChanCfg)
            rc = EditAtmChanCfg(BaseAddress, iChanNum, Side, pCfg->pAtmChanCfg);
        else
        {
            return bb_INV_ATM_CHAN_CFG_USED;
        }

    }
    else if( (pCfg->RepeaterMode != ixf6048_eCHANNEL_IN_REPEATER_MODE ) &&
        (pCfg->ChanMode == ixf6048_ePOS_MODE_CHAN) )
    {
        if (pCfg->pPosChanCfg)
            rc = EditPosChanCfg(BaseAddress, iChanNum, Side, pCfg->pPosChanCfg);
        else
        {
            return bb_INV_POS_CHAN_CFG_USED;
        }
    }

#ifdef UNIT_TEST_6048
    printf("Edit of Channel Cfg at 0x%x - PASSED OK\n", pCfg);
#endif

    return rc;       /* should be bb_NO_ERROR */
}   /* end EditChanCfg */


/***********************************************************************
 * Procedure Name:   EditChanIfCfg
 *
 * Description:      Edit Channel If configuration 
 *
 * Conditions for Use:
 *    Driver is initialized OK
 *    pCfg is non-NULL
 *
 * Notes:
 *    This Sets up the Channel Config that is Common to Rx and Tx Sides
 *
 *
 * PDL:
 *
 * End
 **********************************************************************/
static bb_Error_e EditChanIfCfg(ushort*             BaseAddress,
    uint                ChanNum,
    ixf6048_Side_e      Side ,
    ixf6048_ChanMode_e  ChanMode,
    ixf6048_ChanIfCfg_t *pCfg)
{
    bb_Error_e        rc = bb_NO_ERROR;
    register ushort   RegVal=0;
    volatile register bb_RegPointer_type  pGlobalCnfReg;
    volatile register bb_RegPointer_type  pChanCnfReg;
    volatile register bb_RegPointer_type  pReg;
    register ushort         macroRegVal =0;
    /* Set the Line Speed configuration -- Common to Tx and Rx. */
    if(Side == ixf6048_eSIDE_BOTH)
    {
        pGlobalCnfReg = BaseAddress + ixf6048_GOCNF_OFFSET;
        pChanCnfReg   = BaseAddress + ixf6048_COCNF_CHAN_OFFSET(ChanNum);

        /* Clear the Channel Rate Bits Prior to Write  */
        Ixf6048ClrBit(pChanCnfReg, ixf6048_mCHAN_RATE);
        switch (pCfg->LineSideSpeed)
        {
        case ixf6048_eSINGLE_STS_48C: /* Must be Concat,Single Mode */
        case ixf6048_eSINGLE_STM_16C:
            Ixf6048SetBit(pGlobalCnfReg, ixf6048_bC_MODE);
            Ixf6048SetBit(pChanCnfReg, ixf6048_bCHAN_RATE_OC48);
            break;
        case ixf6048_eSINGLE_STS_48:  /* Must be NonConcat, Single Mode */
        case ixf6048_eSINGLE_STM_16:
            Ixf6048ClrBit(pGlobalCnfReg,ixf6048_bC_MODE);
            Ixf6048SetBit(pChanCnfReg, ixf6048_bCHAN_RATE_OC48);
            break;
        case ixf6048_eSINGLE_STS_12:  /* Must be NonConcat, Single Mode */
        case ixf6048_eSINGLE_STM_4:
            Ixf6048ClrBit(pGlobalCnfReg,ixf6048_bC_MODE);
            Ixf6048SetBit(pChanCnfReg, ixf6048_bCHAN_RATE_OC12);
            break;
        case ixf6048_eSINGLE_STS_12C:   /* Concatenated , Single Mode */
            if(ChanNum == 0)
            {	/* Assign Channel 1 to be the Same as Channel 2 -- See Erata */
                pReg = BaseAddress + ixf6048_COCNF_CHAN_OFFSET(1);
                /* Note: The Following MUST be done for ixf6012 Bug.. Chan(1) Must be the Same as Chan(0) */
                Ixf6048ClrBit(pReg, ixf6048_mCHAN_RATE);
                Ixf6048SetBit(pReg, ixf6048_bCHAN_RATE_OC12);
            }
            Ixf6048SetBit(pGlobalCnfReg,ixf6048_bC_MODE);
            Ixf6048SetBit(pChanCnfReg, ixf6048_bCHAN_RATE_OC12);
            break;
        case ixf6048_eSINGLE_STS_3C:   /* Must be NonConcat, Single Mode */
            Ixf6048SetBit(pGlobalCnfReg,ixf6048_bC_MODE);
            Ixf6048SetBit(pChanCnfReg, ixf6048_bCHAN_RATE_OC3);
            /* Note: The Following MUST be done for ixf6012 Bug.. Chan(1) Must be the Same as Chan(0) */
            if(ChanNum == 0)
            {	/* Assign Channel 1 to be the Same as Channel 2 -- See Erata */
                pReg = BaseAddress + ixf6048_COCNF_CHAN_OFFSET(1);
                /* Note: The Following MUST be done for ixf6012 Bug.. Chan(1) Must be the Same as Chan(0) */
                Ixf6048ClrBit(pReg, ixf6048_mCHAN_RATE);
                Ixf6048SetBit(pReg, ixf6048_bCHAN_RATE_OC3);
            }
            break;
        case ixf6048_eSINGLE_STS_3:   /* Must be NonConcat, Single Mode */
            Ixf6048ClrBit(pGlobalCnfReg,ixf6048_bC_MODE);
            Ixf6048SetBit(pChanCnfReg, ixf6048_bCHAN_RATE_OC3);
            break;
        case ixf6048_eQUAD_STS_12C:   /* Must be Concat, Quad Mode */
        case ixf6048_eQUAD_STM_4C:
            Ixf6048SetBit(pGlobalCnfReg,ixf6048_bC_MODE);
            Ixf6048SetBit(pChanCnfReg, ixf6048_bCHAN_RATE_OC12);
            break;
        case ixf6048_eQUAD_STS_3C:    /* Must be Concat,Quad Mode */
        case ixf6048_eQUAD_STM_1:
            Ixf6048SetBit(pGlobalCnfReg,ixf6048_bC_MODE);
            Ixf6048SetBit(pChanCnfReg, ixf6048_bCHAN_RATE_OC3);
            break;
        case ixf6048_eQUAD_STS_1:     /* Must be Concat, Quad Mode */
            Ixf6048SetBit(pGlobalCnfReg,ixf6048_bC_MODE);
            /* Already Set to OC-1 Above */
            break;
        default:
            return bb_INV_LINE_SPEED_USED;
        }
    }

    /* Initialize Each Side -- Rx and Tx individually*/
    if( (Side == ixf6048_eSIDE_BOTH   )||
        (Side == ixf6048_eSIDE_RECEIVE) )
    {
        pReg = BaseAddress + ixf6048_R_COCNF_CHAN_OFFSET(ChanNum);
        /* Get A copy of the Register to work with */
        RegVal = READ_FROM_HW(pReg);
        WRITE_TO_HW(pReg, 0); /* Clear Register */
        /* Set the RcvLockCnf */
        if(pCfg->RcvLockConfig == ixf6048_eSWITCH_TO_BLUE_CLOCK_ON_ACTIVE_HIGH)
            Ixf6048SetBitVal(RegVal,ixf6048_bRCV_LOCK_CNF);
        else
            Ixf6048ClrBitVal(RegVal,ixf6048_bRCV_LOCK_CNF);
        /* Set the New If Mode */
        /* ixf6048_SET_IF_MODE(RegVal,pCfg->RxLineSideInterface); */

        RegVal =  (uint)(RegVal & ~ixf6048_mIF_MODE    );
        RegVal |= ((pCfg->RxLineSideInterface<< 2)& ixf6048_mIF_MODE);

        /* Set the Clock Divide */
        ixf6048_SET_CO_CNF(RegVal, pCfg->RxTtlClockDivide);
        /* Write the new Value to the Register */
        WRITE_TO_HW(pReg, RegVal);

        /* Set the UTOPIA Configuration Only if POS or ATM Mode */
        /* Set the UTOPIA Configuration Only if POS or ATM Mode */
        if( (ChanMode == ixf6048_eATM_MODE_CHAN) ||
            (ChanMode == ixf6048_ePOS_MODE_CHAN) )
        {
            /* Set the Common Configuration */
            pReg = BaseAddress + ixf6048_R_UICHCNF_CHAN_OFFSET(ChanNum);
            RegVal = READ_FROM_HW(pReg);
            /* Utopia Parity */
            if (pCfg->RxUtopiaParity == ixf6048_eUTOPIA_ODD_PARITY)
                Ixf6048ClrBitVal(RegVal,ixf6048_bPRTY_CNF);
            else
                Ixf6048SetBitVal(RegVal,ixf6048_bPRTY_CNF);

            /* Decode Response Delay */
            if(pCfg->RxUtopiaResponseDelay == ixf6048_eONE_CYCLE_DECODE_RESPONSE_DELAY)
                Ixf6048ClrBitVal(RegVal, ixf6048_bD_R_CNF);
            else
                Ixf6048SetBitVal(RegVal, ixf6048_bD_R_CNF);

            if (pCfg->RxFaPolarity == ixf6048_eTXFA_ACTIVE_HIGH)
                Ixf6048ClrBitVal(RegVal, ixf6048_bF_A_CNF);
            else
                Ixf6048SetBitVal(RegVal, ixf6048_bF_A_CNF);

            /* Set the ATM Specific Configuration */
            if(ChanMode == ixf6048_eATM_MODE_CHAN)
            {  /* RcvBurstCnf Bit */
                if(pCfg->UtopiaAtmChanCfg.RxCellBurstCnf == ixf6048_eCELL_BURST_PASS_THROUGH_MODE)
                    Ixf6048SetBitVal(RegVal, ixf6048_bBURST_CNF);
                else
                    Ixf6048ClrBitVal(RegVal, ixf6048_bBURST_CNF);

                if(pCfg->UtopiaAtmChanCfg.RxDummyHecWord == ixf6048_ePASS_NULL_HEC_WORD)
                    Ixf6048SetBitVal(RegVal, ixf6048_bCELL_STRUCT);
                else
                    Ixf6048ClrBitVal(RegVal, ixf6048_bCELL_STRUCT);
                /* Set the Cell Available Deassertion level */
                ixf6048_SET_C_A_DEASSERT(RegVal, pCfg->UtopiaAtmChanCfg.RxCellAvailDeassertByteNum);
            }
            else /*  (ChanMode == ixf6048_ePOS_MODE_CHAN) */
                SetPosWatermarks(BaseAddress, ChanNum, ixf6048_eSIDE_TRANSMIT, &pCfg->PosWatermarks);

            /* Write the new Value to the R_UICHCNF Register */
            WRITE_TO_HW(pReg, RegVal);
        }
    }

    /* Channel Configuration for the TRANSMIT Side */
    if( (Side == ixf6048_eSIDE_BOTH   )||
        (Side == ixf6048_eSIDE_TRANSMIT) )
    {
        pReg = BaseAddress + ixf6048_T_COCNF_CHAN_OFFSET(ChanNum);
        /* Get A copy of the Register to work with */
        RegVal = READ_FROM_HW(pReg);
        WRITE_TO_HW(pReg, 0); /* Clear the Register */

        /* Set the output PECL Clock Config */
        if (pCfg->XmtPClkOutConfig == ixf6048_eXMT_PECL_CLK_DISABLED)
            Ixf6048SetBitVal(RegVal, ixf6048_bXMT_PCLK_OUT);
        else   /* Enable the output Clock -- This is An Active Low Bit*/
            Ixf6048ClrBitVal(RegVal, ixf6048_bXMT_PCLK_OUT);
        /* Set the New If Mode */
        /* ixf6048_SET_IF_MODE(RegVal,pCfg->TxLineSideInterface); */
        RegVal =  (uint)(RegVal & ~ixf6048_mIF_MODE);
        RegVal |= ((pCfg->TxLineSideInterface<< 2)& ixf6048_mIF_MODE);
        /* Set the new Clock Divide */
        /* PSN_DEBUG */
        /* ixf6048_SET_CO_CNF(RegVal, pCfg->TxTtlClockDivide); */
        RegVal &= ~ixf6048_mCO_CNF;
        RegVal |= (pCfg->TxTtlClockDivide << 5) & ixf6048_mCO_CNF;
        ixf6048_SET_XMT_TIM_REF_CLK_SRC(RegVal, pCfg->TxTimingSource);
        /* Write the new Value to the Register */
        WRITE_TO_HW(pReg, RegVal);

        /* Set the UTOPIA Configuration Only if POS or ATM Mode */
        if( (ChanMode == ixf6048_eATM_MODE_CHAN) ||
            (ChanMode == ixf6048_ePOS_MODE_CHAN) )
        {
            /* Set the Common Configuration */
            pReg = BaseAddress + ixf6048_T_UICHCNF_CHAN_OFFSET(ChanNum);
            RegVal = READ_FROM_HW(pReg);

            /* Utopia Parity */
            if (pCfg->TxUtopiaParity == ixf6048_eUTOPIA_ODD_PARITY)
                Ixf6048ClrBitVal(RegVal,ixf6048_bPRTY_CNF);
            else
                Ixf6048SetBitVal(RegVal,ixf6048_bPRTY_CNF);
            /* Decode Response Delay */
            if(pCfg->TxUtopiaResponseDelay == ixf6048_eONE_CYCLE_DECODE_RESPONSE_DELAY)
                Ixf6048ClrBitVal(RegVal, ixf6048_bD_R_CNF);
            else
                Ixf6048SetBitVal(RegVal, ixf6048_bD_R_CNF);

            if (pCfg->TxFaPolarity == ixf6048_eTXFA_ACTIVE_HIGH)
                Ixf6048ClrBitVal(RegVal, ixf6048_bF_A_CNF);
            else
                Ixf6048SetBitVal(RegVal, ixf6048_bF_A_CNF);

            /* Set the ATM Specific Configuration */
            if(ChanMode == ixf6048_eATM_MODE_CHAN)
            {  /* XmtBurstCnf bit */
                if(pCfg->UtopiaAtmChanCfg.TxCellBurstCnf == ixf6048_eCELL_BURST_PASS_THROUGH_MODE)
                    Ixf6048SetBitVal(RegVal, ixf6048_bBURST_CNF);
                else
                    Ixf6048ClrBitVal(RegVal, ixf6048_bBURST_CNF);

                if(pCfg->UtopiaAtmChanCfg.TxDummyHecWord == ixf6048_ePASS_