ixf6048.c

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

            MultiDeviceCheck = ixf6048_eSINGLE_UTOPIA_DEV;
            break;

        case ixf6048_eUTOPIA_L3_4_X_8_BIT:  /* Level 3 with 4 independent 8-bit buses */
            /* Set the Tx Utopia data bus widths to 8 Bit */
            /*  and Set the Tx QuadMode bits to 1 */
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /*ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_8BIT);*/
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_8BIT));

            /* Always set the Utopia Interface to a Quad Device for this mode */
            MultiDeviceCheck = ixf6048_eMULTIPLE_UTOPIA_DEVS;
            break;

        case ixf6048_eUTOPIA_L2_16_BIT:     /* Level 2 with 16-bit data bus */
            /* Set the Tx Utopia data bus widths to 16 Bit */
            /*  and Set the Tx QuadMode bits to 0 */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_16BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_16BIT));

            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eSINGLE_UTOPIA_DEV;
            break;

        case ixf6048_eUTOPIA_L2_4_X_16_BIT: /* Level 2 with 4 independant 16-bit data buses */
            /* Set the Tx Utopia data bus widths to 16 Bit */
            /*  and Set the Tx QuadMode bits to 1 */
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_16BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_16BIT));
            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eMULTIPLE_UTOPIA_DEVS;
            break;

        case ixf6048_eUTOPIA_L2_8_BIT:     /* Level 2 with 8-bit data bus */
            /* Set the Tx Utopia data bus widths to 8 Bit */
            /*  and Set the Tx QuadMode bits to 0 */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_8BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_8BIT));
            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eSINGLE_UTOPIA_DEV;
            break;
        case ixf6048_eUTOPIA_L2_4_X_8_BIT: /* Level 2 with 4 - 8-bit data buses */
            /* Set the Rcv  Utopia data bus widths to 8 Bit */
            /*  and Set the Rcv QuadMode bits to 0 */
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_8BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_8BIT));
            UtopiaWidthIs8Bit = TRUE;
            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eMULTIPLE_UTOPIA_DEVS;
            break;

        case ixf6048_eUTOPIA_L1_4_X_8_BIT: /* Level 1 with 4 independent 8-bit buses */
            /* Set the Tx Utopia data bus widths to 8 Bit */
            /*  and Set the Tx QuadMode bits to 1 */
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_8BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_8BIT));

            /* Always set the Utopia Interface to a Quad Device for this mode */
            MultiDeviceCheck = ixf6048_eMULTIPLE_UTOPIA_DEVS;
            break;

        default:
            return bb_INV_UTOPIA_INTERFACE_USED;
        } /* end Switch */

        if(pCfg->TxUtopiaSmallMemCfg == ixf6048_eSMALL_MEM_CHAN_0_FIFO_2K)
            Ixf6048SetBit(pUicnfReg, ixf6048_bXMT_SMALL_MEM);
        else
            Ixf6048ClrBit(pUicnfReg, ixf6048_bXMT_SMALL_MEM);

        /* Ensure that the MultiDevice bit is Configured Correctly. */
        if(pCfg->TxUtopiaMultiPhy != MultiDeviceCheck)
        {
            pCfg->TxUtopiaMultiPhy = MultiDeviceCheck;
        }

        /* Configure how RXPFA is driven */
        if (pCfg->XmtMPhyDevCnf == ixf6048_eOUTPUT_ONLY_DRIVEN_WHEN_SELECTED)
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_M_PHY_DEV_CNF);
        else  /* Can only be used if the Interface is NOT shared */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_M_PHY_DEV_CNF);

        /* PSN_ADDED for B1 Release */
        /* Set the Behavior for Tristating the Rx UTOPIA interface */
        if(pCfg->XmtUOutEnCnf == ixf6048_eUTOPIA_OUT_EN_CNF_NOT_DISABLED_INDEPENDANTLY)
            Ixf6048SetBit(pGocnfReg, ixf6048_bXMT_U_OUT_EN_CNF);
        else
            Ixf6048ClrBit(pGocnfReg, ixf6048_bXMT_U_OUT_EN_CNF);

        /* PSN_END B1 Release Changes */

    } /* End if( Transmit or Both Side )*/

    /* Always Set the Utopia Base Address regardless of Side*/
    /* Mask Address Bits then write new Address */
    Ixf6048ClrBit(pGocnfReg, ixf6048_mUTOPIA_ADDR_BASE);
    Ixf6048SetBit(pGocnfReg, (pCfg->UtopiaDevBaseAddress & ixf6048_mUTOPIA_ADDR_BASE));

    return bb_NO_ERROR;
}

/***********************************************************************
 * Procedure Name: EditPosChipCfg  
 *
 * Description: This function sets the Configuration for the Utopia
 *              interface when in POS mode. 
 *
 * Conditions for Use:
 *    Driver is initialized OK
 *    pPosChipCfg is non-NULL
 *
 * Notes:
 *    The bits are Always initialized regardless of whether POS
 *    mode is selected for any of the channels. 
 *    The user must ensure that the  ixf6048_PosChipCfg_t contains 
 *    valid data.
 *
 *
 * End
 **********************************************************************/
static bb_Error_e EditPosChipCfg (ushort*               BaseAddress,
    ixf6048_Side_e        Side,
    ixf6048_PosChipCfg_t* pPosChipfg)
{
    bb_Error_e          rc = bb_NO_ERROR;
    register ushort*    pRxReg;
    register ushort*    pTxReg;
    register ushort     RxRegVal = 0;
    register ushort     TxRegVal = 0;

    if( (Side == ixf6048_eSIDE_BOTH) ||
        (Side == ixf6048_eSIDE_RECEIVE) )
    {
        /* Point to the Receive UTOPIA Configuration Register */
        pRxReg = BaseAddress +  ixf6048_R_UICNF_OFFSET;
        /* Get the Current Config Values */
        RxRegVal = READ_FROM_HW(pRxReg);

        /* clear all Rx Configuration bits */
        Ixf6048ClrBitVal(RxRegVal, (ixf6048_bRCV_VAL2_CNF |
            ixf6048_bRCV_XMT_SEL_MODE |
            ixf6048_bRX_TX_DIR_STAT_CNF |
            ixf6048_bRCV_VAL_CNF |
            ixf6048_bRCV_FIF_EMPT_EOF));

        /* Configure the Rx Selection Mode Bit 0*/
        if(pPosChipfg->RxPosUtopiaSelMode == ixf6048_ePOS_UTOPIA_MEMORY_MAPPED)
            Ixf6048SetBitVal(RxRegVal,ixf6048_bRCV_XMT_SEL_MODE);
        /* Configure the Rx Direct Status Indication config - Bit5*/
        if (pPosChipfg->RxFaStatus == ixf6048_eFA_MULTIPLEXED_STATUS_POLLING)
            Ixf6048SetBitVal(RxRegVal,ixf6048_bRX_TX_DIR_STAT_CNF);
        /* Configure the Receive Value Output (Rx-Bit7)*/
        if (pPosChipfg->RxValDeassertAtEop == ixf6048_eRXVAL_DEASSERT_ON_FIFO_EMPTY)
            Ixf6048SetBitVal(RxRegVal, ixf6048_bRCV_VAL_CNF);
        /* Configure the Assertion Condition for the Receive FIFO  (Rx-Bit6)*/
        if ( pPosChipfg->RxFaDeassertOnLow == ixf6048_eRXFA_DEASSERT_ON_LOW_IF_NO_EOF)
            Ixf6048SetBitVal(RxRegVal, ixf6048_bRCV_FIF_EMPT_EOF);
        /* PSN_ADDED B1 Release */
        /* Configure the Blocking of the REceive Interface */
        if(pPosChipfg->RxVal2Cnf == ixf6048_eRCV_VAL2_CNF_READ_BLOCKED_IF_EOF_ONLY)
            Ixf6048SetBitVal(RxRegVal, ixf6048_bRCV_VAL2_CNF);
        /* PSN_END B1 Release Changes */

        /* Now write the new Configuration values */
        WRITE_TO_HW(pRxReg, RxRegVal);
        /* Now set the Rx Fifo Restart levels */
        pRxReg  = BaseAddress + ixf6048_R_UIIML_OFFSET;
        WRITE_TO_HW(pRxReg, (pPosChipfg->RxFifoRestartLevel & ixf6048_mR_UIIML));
    }

    if( (Side == ixf6048_eSIDE_BOTH) ||
        (Side == ixf6048_eSIDE_TRANSMIT) )
    {
        /* Transmit Side Config */
        pTxReg  = BaseAddress +  ixf6048_T_UICNF_OFFSET;
        TxRegVal= READ_FROM_HW(pTxReg);

        /* clear all Tx Configuration bits */
        Ixf6048ClrBitVal(TxRegVal, (ixf6048_bRCV_XMT_SEL_MODE |
            ixf6048_bRX_TX_DIR_STAT_CNF |
            ixf6048_XMT_FIF_EMPT_EOF) );

        /* Configure the Tx Selection Mode Bit 0*/
        if(pPosChipfg->TxPosUtopiaSelMode == ixf6048_ePOS_UTOPIA_MEMORY_MAPPED)
            Ixf6048SetBitVal(TxRegVal, ixf6048_bRCV_XMT_SEL_MODE);

        /* Configure the Tx Direct Status Indication config - Bit5*/
        if (pPosChipfg->TxFaStatus == ixf6048_eFA_MULTIPLEXED_STATUS_POLLING)
            Ixf6048SetBitVal(TxRegVal, ixf6048_bRX_TX_DIR_STAT_CNF);
        /* Configure when the Tx FIFO can start Tx of a new packet (Tx-Bit6)*/
        if ( pPosChipfg->TxEofEmpty == ixf6048_eTX_AT_GT_MIN_LEVEL_ONLY)
            Ixf6048SetBitVal(TxRegVal, ixf6048_XMT_FIF_EMPT_EOF);

        /* Write new configuration values to Registers */
        WRITE_TO_HW(pTxReg, TxRegVal);

        /* Now set the Rx and Tx Fifo Restart levels */
        pTxReg  = BaseAddress + ixf6048_T_UIIML_OFFSET;
        WRITE_TO_HW(pTxReg, (pPosChipfg->TxFifoRestartLevel & ixf6048_mT_UIIML));
    }

#ifdef UNIT_TEST_6048
    printf("Edit of POS Chip Cfg at 0x%x - PASSED OK\n", pPosChipfg);
#endif

    return rc;       /* should be bb_NO_ERROR */
}  /* End EditPosChipCfg */

/***********************************************************************
 * Procedure Name: InitChanCfg
 *
 * Description:Initialize Chip
 *
 * Conditions for Use:
 *    All Data passed to function is Assumed Valid. 
 *
 * Note:
 *    bb_InitDriver - has completed OK
 *
 *
 * End
 **********************************************************************/
static bb_Error_e InitChanCfg(ushort*            BaseAddress,
    ixf6048_Side_e     Side,
    ixf6048_ChipCfg_t* pChipCfg)
{
    bb_Error_e         rc       = bb_NO_ERROR;
    ixf6048_ChanCfg_t* pChanCfg = NULL;      /* -> Specific cfg */
    int                iMaxNumChans = SINGLE_CHANNEL_MODE;
    int                ChanNum;

    /* Check for Qmode to Determine how many channels are assigned. */
    if(pChipCfg->NumChanCfg != ixf6048_eSINGLE_CHAN)
        iMaxNumChans = QUAD_CHANNEL_MODE;

    for (ChanNum=0; ChanNum < iMaxNumChans; ++ChanNum)
    {
        if (pChipCfg->pChanCfg[ChanNum])
        {
            pChanCfg =  pChipCfg->pChanCfg[ChanNum];
            /* Edit the Configuration of Each Assigned Channel Both Rx and Tx*/
            rc =  EditChanCfg(BaseAddress, ChanNum, Side, pChanCfg);
            if (rc != bb_NO_ERROR)
                return rc;
        }
        else if (ChanNum == 0)
        {  /* If Channel 0 fails then there is a Problem so Exit */
            return bb_INVALID_CHAN_CFG;
        }
        else /* Must be Channel 1-3, with No Config so Simply Disable */
        {

        }
    }
    return rc;
}
#endif
/***********************************************************************
 * Procedure Name:   EditChanCfg
 *
 * Description:      Edit Channel configuration
 *
 * Conditions for Use:
 *    Driver is initialized OK
 *    pCfg is non-NULL
 *
 * Notes:
 *    pCfg->ChanMode is the Same Value for both Tx and Rx Sides.
 *      
 *    Definitions of Structures used in this function
 *      ixf6048_ChanIfCfg_t*  pChanIfCfg;                                     
 *      ixf6048_OhtChanCfg_t* pOhtChanCfg;
 *      ixf6048_AtmChanCfg_t* pAtmChanCfg;    NULL if not ATM
 *      ixf6048_PosChanCfg_t* pPosChanCfg;    NULL if not POS
 *
 *
 * End
 **********************************************************************/
static bb_Error_e EditChanCfg (ushort*            BaseAddress, 
    int                iChanNum,
    ixf6048_Side_e     Side,
    ixf6048_ChanCfg_t* pCfg)
{
    bb_Error_e       rc = bb_NO_ERROR;
    register ushort* pReg;
    ushort			 RegVal=0;
    /* Set the ChanMode for this Channel -- Rx and Tx */
    if( (Side == ixf6048_eSIDE_RECEIVE) ||
        (Side == ixf6048_eSIDE_BOTH   ) )
    {
        /* PSN_ADDED for B1 Release  -- NOTE: RegVal Addition*/
        pReg = BaseAddress + ixf6048_R_COCNF_CHAN_OFFSET(iChanNum);
        RegVal = READ_FROM_HW(pReg);
        Ixf6048ClrBitVal(RegVal, ixf6048_mCHAN_MODE); /* Clear ChanMode bits */
        Ixf6048SetBitVal(RegVal, (pCfg->ChanMode & ixf6048_mCHAN_MODE));
        if(pCfg->TrScrEn == ixf6048_eTR_SCR_EN_SCRAMBLER_ENABLED)
            Ixf6048SetBitVal(RegVal, ixf6048_bRCV_TRANS_DESCR_EN);
        else
            Ixf6048ClrBitVal(RegVal, ixf6048_bRCV_TRANS_DESCR_EN);