ixf6048.c

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

    else
        Ixf6048ClrBit((BaseAddress + ixf6048_MACNF_OFFSET), ixf6048_bBYTE_CHG_UPD_DSBL);

    /* I/O Pin Config and PECL MSB config */
    /* Clear Related bits in Reg Val */
    Ixf6048ClrBit((BaseAddress + ixf6048_GOCNF_OFFSET), ixf6048_bGEN_IO_VAL |
        ixf6048_bGEN_IO_MODE |
        ixf6048_bXMT_PECL_MSB_CNF|
        ixf6048_bRCV_PECL_MSB_CNF);
    /* Set the GENIO Input/output Config bits */
    if (pCfg->GenIOVal == ixf6048_eGEN_IO_VAL_HIGH)
        Ixf6048SetBit((BaseAddress + ixf6048_GOCNF_OFFSET), ixf6048_bGEN_IO_VAL);
    if (pCfg->GenIOMode == ixf6048_eGEN_IO_MODE_OUTPUT)
        Ixf6048SetBit((BaseAddress + ixf6048_GOCNF_OFFSET), ixf6048_bGEN_IO_MODE);
    /* Set the PECL MSB Bit order for Rx and Tx */
    if (pCfg->XmtPeclMsbCnf == ixf6048_ePECL_MSB_CNF_BIT_PN_0)
        Ixf6048SetBit((BaseAddress + ixf6048_GOCNF_OFFSET), ixf6048_bXMT_PECL_MSB_CNF);
    if (pCfg->RcvPeclMsbCnf == ixf6048_ePECL_MSB_CNF_BIT_PN_0)
        Ixf6048SetBit((BaseAddress + ixf6048_GOCNF_OFFSET), ixf6048_bRCV_PECL_MSB_CNF);

    /* PSN_END B1 Release Changes */

    rc = EditUtopiaChipCfg(BaseAddress, Side, &pCfg->UtopiaChipCfg);

    /* Set the Orderwire Configuration bits */
    RegVal = 0;

    if(pCfg->OrderWirePulseByteLocn == ixf6048_eMSB_SAME_CLK_CYCLE_AS_PULSE)
        Ixf6048SetBitVal(RegVal,ixf6048_bOW_PlS_CNF);

    if(pCfg->OverheadPortMode == ixf6048_eOH_PORT_LOGICAL_INTERFACE_NUM3)
        Ixf6048SetBitVal(RegVal, ixf6048_bOH_PORT_MODE);

    /* Set the bits to the Register */
    WRITE_TO_HW((BaseAddress + ixf6048_OHPCNF_OFFSET), RegVal);

    /* Set the Rx and Tx Frame Pulse Bytes */
    pReg = BaseAddress + ixf6048_R_FPCNF_OFFSET;
    WRITE_TO_HW(pReg, (pCfg->RxFramePulseByteNum & ixf6048_mRCV_FPI_CNF));

    RegVal = 0;
    pReg = BaseAddress + ixf6048_T_FPCNF_OFFSET;
    macroRegVal = READ_FROM_HW(pReg);
    SET_XMT_FRAME_PULSE_CNF(macroRegVal, pCfg->TxFramePulseOutByteNum, 
        pCfg->TxFramePulseInByteNum);

    /* Set the Clock Polarity bits to the Registers */
    pReg = BaseAddress + ixf6048_OCPCNF_OFFSET;
    WRITE_TO_HW(pReg, (pCfg->OutClockPolarity & ixf6048_mOCPCNF));

    pReg = BaseAddress + ixf6048_ICPCNF1_OFFSET;
    WRITE_TO_HW(pReg, (pCfg->InClockPolarity1));

    pReg = BaseAddress + ixf6048_ICPCNF2_OFFSET;
    WRITE_TO_HW(pReg, (pCfg->InClockPolarity2 & ixf6048_OCPCNF2_MASK));

    /* Build the Register Setting for the Non Concat Config */
    /* Set the Non-Concatenation Mode Configuration  -- Set Regardless of Concat mode */
    pReg = BaseAddress + ixf6048_NCMODECNF_OFFSET;
    RegVal = 0;
    if (pCfg->NonconcatModeCnfg.J0MuxConfig == ixf6048_eC0_BYTES_OVER_WRITTEN)
        RegVal |= ixf6048_bJ0_MUX_CNF;

    if (pCfg->NonconcatModeCnfg.BWMuxConfig == ixf6048_eBYTE_INTERLEAVED)
        RegVal |= ixf6048_bB_W_MUX_CNF;

    if (pCfg->NonconcatModeCnfg.BWDeMuxConfig == ixf6048_eBYTE_INTERLEAVED)
        RegVal |= ixf6048_bB_W_DMX_CNF;

    /* Set the new Cnfg Value to the Register */
    WRITE_TO_HW(pReg, RegVal);

    /* Set the Line Side Parity Configuration */
    RegVal = 0;
    if(pCfg->LineSideParityConfig.PrtyModeConfig == ixf6048_ePARITY_PROTECTS_PARALLEL_DATA_BUS_AND_FRAME_PULSE) 
        Ixf6048SetBitVal(RegVal, ixf6048_bPRTY_MODE_CNF);
    if(pCfg->LineSideParityConfig.RxParityConfig == ixf6048_eEVEN_PARITY)
        Ixf6048SetBitVal(RegVal, ixf6048_bRCV_PRTY_CNF);
    if(pCfg->LineSideParityConfig.TxParityConfig == ixf6048_eEVEN_PARITY)
        Ixf6048SetBitVal(RegVal, ixf6048_bXMT_PRTY_CNF);
    /* Now Set the New Config Values to the LineSideParity Register */
    pReg = BaseAddress + ixf6048_LSPCNF_OFFSET;
    WRITE_TO_HW(pReg, RegVal);

    /* Always Set the Pos Chip Configuration. 
    -- if No POS mode being used then these should be set to Defaults (0) */
    rc = EditPosChipCfg( BaseAddress, Side, &pCfg->PosChipCfg);

#ifdef UNIT_TEST_6048
    printf("Edit of Chip Level Cfg at 0x%x - PASSED OK\n", pCfg);
#endif

    return rc;       /* should be bb_NO_ERROR */
} /* End EditChipLevelCfg */

/***********************************************************************
 * Procedure Name: EditUtopiaChipCfg  
 *
 * Description: This function sets the Configuration for the Chip Level
 *              Utopia interface.
 *
 * Conditions for Use:
 *    Driver is initialized OK
 *    pCfg is non-NULL
 *
 * Notes:
 *    The user must ensure that the  ixf6048_UtopiaCfg_t contains 
 *    valid data.
 *    This application only uses "Side" Param ixf6048_eSIDE_BOTH, 
 *    but it is included for future flexibility
 *    
 *
 * End
 **********************************************************************/
static bb_Error_e EditUtopiaChipCfg(ushort*             BaseAddress,
    ixf6048_Side_e       Side,
    ixf6048_UtopiaChipCfg_t *pCfg)
{
    ixf6048_UtopiaMultiPhy_e MultiDeviceCheck;
    boolean UtopiaWidthIs8Bit = FALSE;
    register ushort* pUicnfReg;
    register ushort* pGocnfReg;

    /* PSN_ADDED -- Note the *pReg Changes */

    pGocnfReg = BaseAddress + ixf6048_GOCNF_OFFSET;
    if( (Side == ixf6048_eSIDE_BOTH) ||
        (Side == ixf6048_eSIDE_RECEIVE) )
    {
        /* Set the Utopia Interface Configuration for Rx */
        pUicnfReg = BaseAddress + ixf6048_R_UICNF_OFFSET;
        switch(pCfg->RxUtopiaInterface)
        {
        case ixf6048_eUTOPIA_L3_64_BIT_USING_TTL_PINS: /* U64Mode = 0 */
        case ixf6048_eUTOPIA_L3_64_BIT_USING_SOH_PINS: /* U64Mode = 1 */
            /* Set the Rcv Utopia data bus widths to 64 Bit */
            /*  and Set the Rcv QuadMode bits to 0 */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_SINGLE_64BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_SINGLE_64BIT));

            /* Clr/Set the U64Mode Bit in GOCNF Reg */
            if( pCfg->RxUtopiaInterface == ixf6048_eUTOPIA_L3_64_BIT_USING_TTL_PINS)
                Ixf6048ClrBit(pGocnfReg, ixf6048_bU64_MODE);
            else /* Must be ixf6048_eUTOPIA_L3_64_BIT_USING_SOH_PINS */
                Ixf6048SetBit(pGocnfReg, ixf6048_bU64_MODE);

            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eSINGLE_UTOPIA_DEV;
            break;
        case ixf6048_eUTOPIA_L3_32_BIT: /* Level 3 with 32-bit data bus */
            /* Set the Rcv  Utopia data bus widths to 32 Bit */
            /*  and Set the Rcv QuadMode bits to 0 */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_SINGLE_32BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_SINGLE_32BIT));
            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eSINGLE_UTOPIA_DEV;
            break;

        case ixf6048_eUTOPIA_L3_4_X_8_BIT:  /* Level 3 with 4 independent 8-bit buses */
            /* Set the Rcv Utopia data bus widths to 8 Bit */
            /*  and Set the Rcv QuadMode bits to 1 */
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_8BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_8BIT));
            UtopiaWidthIs8Bit = TRUE;
            /* Always set the Utopia Interface to a Quad Device for this mode */
            MultiDeviceCheck = ixf6048_eMULTIPLE_UTOPIA_DEVS;
            break;

        case ixf6048_eUTOPIA_L2_16_BIT:     /* Level 2 with 16-bit data bus */
            /* Set the Rcv and Tx Utopia data bus widths to 16 Bit */
            /*  and Set the Rcv/Tx QuadMode bits to 0 */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /*ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_16BIT);*/
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_16BIT));
            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eSINGLE_UTOPIA_DEV;
            break;

        case ixf6048_eUTOPIA_L2_4_X_16_BIT: /* Level 2 with 4 independant 16-bit data buses */
            /* Set the Rcv Utopia data bus widths to 16 Bit */
            /*  and Set the Rcv QuadMode bits to 1 */
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_16BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_16BIT));
            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eMULTIPLE_UTOPIA_DEVS;
            break;

        case ixf6048_eUTOPIA_L2_8_BIT:     /* Level 2 with 8-bit data bus */
            /* Set the Rcv  Utopia data bus widths to 8 Bit */
            /*  and Set the Rcv QuadMode bits to 0 */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /*ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_8BIT);*/
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_8BIT));
            UtopiaWidthIs8Bit = TRUE;
            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eSINGLE_UTOPIA_DEV;
            break;

        case ixf6048_eUTOPIA_L2_4_X_8_BIT: /* Level 2 with 4 - 8-bit data buses */
            /* Set the Rcv  Utopia data bus widths to 8 Bit */
            /*  and Set the Rcv QuadMode bits to 0 */
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_8BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_8BIT));
            UtopiaWidthIs8Bit = TRUE;
            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eMULTIPLE_UTOPIA_DEVS;
            break;
        case ixf6048_eUTOPIA_L1_4_X_8_BIT: /* Level 1 with 4 independent 8-bit buses */
            /* Set the Rcv Utopia data bus widths to 8 Bit */
            /*  and Set the Rcv QuadMode bits to 1 */
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_QUAD_SINGLE_8BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_QUAD_SINGLE_8BIT));
            UtopiaWidthIs8Bit = TRUE;
            /* Always set the Utopia Interface to a Quad Device for this mode */
            MultiDeviceCheck = ixf6048_eMULTIPLE_UTOPIA_DEVS;
            break;

        default:
            return bb_INV_UTOPIA_INTERFACE_USED;
        } /* end Switch -- RxUtopiaInterface */

        if (UtopiaWidthIs8Bit == TRUE)
        {   /* In 8 Bit Mode RcvAtmHEC is used to configure Extra Byte information */
            if(pCfg->RcvAtmHecConfig == ixf6048_eEXTRA_BYTE_IS_STATUS)
                Ixf6048SetBit(pUicnfReg, ixf6048_bRCV_ATM_HEC);
            else
                Ixf6048ClrBit(pUicnfReg, ixf6048_bRCV_ATM_HEC);
        }
        if(pCfg->RxUtopiaSmallMemCfg == ixf6048_eSMALL_MEM_CHAN_0_FIFO_2K)
            Ixf6048SetBit(pUicnfReg, ixf6048_bRCV_SMALL_MEM);
        else
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRCV_SMALL_MEM);

        /* Ensure that the MultiDevice bit is Configured Correctly. */
        if(pCfg->RxUtopiaMultiPhy != MultiDeviceCheck)
        {
            pCfg->RxUtopiaMultiPhy = MultiDeviceCheck;
        }
        /* Configure how RXPFA is driven */
        if (pCfg->RcvMPhyDevCnf == ixf6048_eOUTPUT_ONLY_DRIVEN_WHEN_SELECTED)
            Ixf6048SetBit(pUicnfReg, ixf6048_bRX_TX_M_PHY_DEV_CNF);
        else  /* Can only be used if the Interface is NOT shared */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_M_PHY_DEV_CNF);

        /* Set the behaviour of unused pins */
        if(pCfg->UnusedUtopiaPinsImp == ixf6048_eUNUSED_UTOPIA_PINS_HIGH_IMP)
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRCV_TEST_O_EN);
        else /* (pCfg->UnusedUtopiaPinsImp == ixf6048_eUNUSED_UTOPIA_PINS_NOT_HIGH_IMP) */
            Ixf6048SetBit(pUicnfReg, ixf6048_bRCV_TEST_O_EN);

        /* PSN_ADDED for B1 Release */
        /* Set the Behavior for Tristating the Rx UTOPIA interface */
        if(pCfg->RcvUOutEnCnf == ixf6048_eUTOPIA_OUT_EN_CNF_NOT_DISABLED_INDEPENDANTLY)
            Ixf6048SetBit(pGocnfReg, ixf6048_bRCV_U_OUT_EN_CNF);
        else
            Ixf6048ClrBit(pGocnfReg, ixf6048_bRCV_U_OUT_EN_CNF);
        /* PSN_END B1 Release Changes */

    } /* End if( Receive or Both Side )*/

    if( (Side == ixf6048_eSIDE_BOTH) ||
        (Side == ixf6048_eSIDE_TRANSMIT) )
    {
        /* Set the Utopia Interface Configuration for Rx */
        pUicnfReg = BaseAddress + ixf6048_T_UICNF_OFFSET;
        switch(pCfg->TxUtopiaInterface)
        {

        case ixf6048_eUTOPIA_L3_64_BIT_USING_TTL_PINS: /* U64Mode = 0 */
        case ixf6048_eUTOPIA_L3_64_BIT_USING_SOH_PINS: /* U64Mode = 1 */

            /* Set the Tx Utopia data bus widths to 64 Bit */
            /*  and Set the Rcv/Tx QuadMode bits to 0 */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_SINGLE_64BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_SINGLE_64BIT));

            /* Clr/Set the U64Mode Bit in GOCNF Reg */
            if( pCfg->TxUtopiaInterface == ixf6048_eUTOPIA_L3_64_BIT_USING_TTL_PINS)
                Ixf6048ClrBit(pGocnfReg, ixf6048_bU64_MODE);
            else /* Must be ixf6048_eUTOPIA_L3_64_BIT_USING_SOH_PINS */
                Ixf6048SetBit(pGocnfReg, ixf6048_bU64_MODE);

            /* Always set the Utopia Interface to a Single Device for this mode */
            MultiDeviceCheck = ixf6048_eSINGLE_UTOPIA_DEV;
            break;

        case ixf6048_eUTOPIA_L3_32_BIT: /* Level 3 with 32-bit data bus */
            /* Set the Tx Utopia data bus widths to 32 Bit */
            /*  and Set the Tx QuadMode bits to 0 */
            Ixf6048ClrBit(pUicnfReg, ixf6048_bRX_TX_U_QUAD);
            /* ixf6048_SET_U_WIDTH(*pUicnfReg, ixf6048_U_WIDTH_SINGLE_32BIT); */
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) & ~ixf6048_mRX_TX_U_WIDTH));
            WRITE_TO_HW(pUicnfReg, (READ_FROM_HW(pUicnfReg) | ixf6048_U_WIDTH_SINGLE_32BIT));

            /* Always set the Utopia Interface to a Single Device for this mode */