ixf6048d.h

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/* High Order Path G1 RDI Detection Count:
                  3,5,10,16 consecutive frames - R_HPT_C1 15:14 */
typedef enum   
{
   ixf6048_eHPT_RDI_DETECT_ON_3_G1_BYTES = 0,
   ixf6048_eHPT_RDI_DETECT_ON_5_G1_BYTES,
   ixf6048_eHPT_RDI_DETECT_ON_10_G1_BYTES,
   ixf6048_eHPT_RDI_DETECT_ON_16_G1_BYTES
} ixf6048_HptRdiDetect_e;

/* Config detection of Rx HPT RDI Enhanced, or not
                  R_HPT_C1 bit 13, and Table 1 on Pg 99 */
typedef enum   
{
   ixf6048_eDETECT_NON_ENHANCED_HPT_RDI=0,
   ixf6048_eDETECT_ENHANCED_HPT_RDI
} ixf6048_DetectEnhancedHptRdi_e;

/* HPT Signal Label Mismatch Count - R_HPT_C1 bit 12 */
typedef enum   
{
   ixf6048_eHPT_SL_MISMATCH_ON_3_C2 = 0,
   ixf6048_eHPT_SL_MISMATCH_ON_5_C2
} ixf6048_HptSlMismatchCnt_e;

/* Setting of the HP-SLM alarm when the receive C2 signal label is unstable
      -- R_HPT_C1 bit 11 */
typedef enum   
{
   ixf6048_eSLM_ALARM_INDEPENDANT_OF_C2_UNSTABLE=0,
   ixf6048_eFORCE_HPT_SLM_ALARM_ON_C2_UNSTABLE
} ixf6048_HpSlmOnC2Config_e;


/* B3 error counter counts Bit or Block errors
                  R_HPT_C1 bit 10 */
typedef enum   
{
   ixf6048_eCOUNT_B3_BIT_ERRORS = 0,
   ixf6048_eCOUNT_B3_BLOCK_ERRORS
} ixf6048_B3CntrCfg_e;

/* HPT REI error counter counts Bit or Block errors
                  R_HPT_C1 bit 9 */
typedef enum   
{
   ixf6048_eCOUNT_HPT_REI_BIT_ERRORS = 0,
   ixf6048_eCOUNT_HPT_REI_BLOCK_ERRORS
} ixf6048_HptReiCntrCfg_e;

/* Config 2 fixed stuff columns (30 & 59) as part
                  of payload, or not (for STS-1/STM-0 mode only)
                  R_HPT_C1 bit 8, T_HPT_C bit 14 */
typedef enum   
{
   ixf6048_eCOLS_30_59_PAYLOAD = 0,   /* Part of the payload */
   ixf6048_eCOLS_30_59_STUFF          /* Fixed stuff columns */
} ixf6048_Cols30_59_e;

/* Enable/Disable HPT RDI on ATM Loss of Cell Delineation (LCD)
                  R_HPT_C1 bit 7 */
typedef enum   
{
   ixf6048_eDISABLE_HPT_RDI_ON_ATM_LCD=0,
   ixf6048_eENABLE_HPT_RDI_ON_ATM_LCD
} ixf6048_HptRdiOnAtmLcd_e;

/* Config HPT RDI on HPT Signal Label mismatch, as
                  Connectivity Defect, or Payload Defect, or ignore.
                  R_HPT_C1 6:5 */
typedef enum   
{
   ixf6048_eDISABLE_HPT_RDI_ON_HPT_SLM = 0,   /*  SLM does not set HPT RDI */
   ixf6048_eHPT_SLM_SETS_HPT_RDI_CON_DEF = 2, /* SLM is RDI Connectivity Defect */
   ixf6048_eHPT_SLM_SETS_HPT_RDI_PAY_DEF = 3 /*  SLM is RDI Payload Defect */
} ixf6048_HptRdiOnHptSlm_e;

/* Enable/Disable HPT RDI on J1 string mismatch
                  R_HPT_C1 bit 4 */
typedef enum   
{
   ixf6048_eDISABLE_HPT_RDI_ON_J1_MISMATCH = 0,
   ixf6048_eENABLE_HPT_RDI_ON_J1_MISMATCH
} ixf6048_HptRdiOnJ1Mismatch_e;


/* Enable/Disable HPT RDI on HPT Unequipped alarm,
                  as Connectivity Defect - R_HPT_C1 bit 3 */
typedef enum   
{
   ixf6048_eDISABLE_HPT_RDI_ON_HPT_UNEQ=0,
   ixf6048_eENABLE_HPT_RDI_ON_HPT_UNEQ
} ixf6048_HptRdiOnHptUneq_e;

/* Config generation of (enhanced or not) HPT RDI - R_HPT_C1 2:1
                  Values are:
                     Non-enhanced G1 RDI bits: RDI = '100'; no RDI = '000'
                     Non-enhanced G1 RDI bits: RDI = '111'; no RDI = '011'
                     Enhanced G1 RDI bits: See Table 1 on Pg 99 */
typedef enum   
{
   ixf6048_eGEN_HPT_RDI_AS_100 = 0,
   ixf6048_eGEN_HPT_RDI_AS_111 = 1,
   ixf6048_eGEN_ENHANCED_HPT_RDI = 2
} ixf6048_GenHptRdiCfg_e;

/* Config value of G1 spare bit at RPAL output,
                  as a 0 or a 1 - Pg R_HPT_C1 bit 0 */
typedef enum   
{
   ixf6048_eG1_SPARE_BIT_IS_0 = 0,
   ixf6048_eG1_SPARE_BIT_IS_1
} ixf6048_G1SpareBit_e;

/* Configure whether J1 CRC7 error masks J1 Mismatch
                  R_HPT_C2 bit 13 */
typedef enum   
{
   ixf6048_eJ1_CRC7_AND_MISMATCH_SEP=0, /* CRC7 and Mismatch error are separate */
   ixf6048_eJ1_CRC7_MASKS_MISMATCH      /*CRC7 error masks Mismatch error */
} ixf6048_J1Crc7Mismatch_e;

/* Configure whether J1 Unstable sets J1 Mismatch
                  R_HPT_C2 bit 12 */
typedef enum   
{
   ixf6048_eJ1_UNSTABLE_AND_MISMATCH_SEP=0, /* J1 Unstable & Mismatch separate */
   ixf6048_eJ1_UNSTABLE_SETS_MISMATCH       /* J1 Unstable sets J1 Mismatch */
} ixf6048_J1UnstableMismatch_e;

/* Configure num of consecutive, identical J1 strings to be
                  considered stable and accepted - R_HPT_C2 bit 11 */
typedef enum   
{
   ixf6048_eJ1_STABLE_AFTER_3 = 0,    /* J1 stable after 3 consecutive strings */
   ixf6048_eJ1_STABLE_AFTER_5         /* J1 stable after 5 consecutive strings */
} ixf6048_J1StableCnt_e;


/* Configure Expected J1 format - R_HPT_C2 10:8 */
/* Note that ixf6048_RxJnFormat_e is Defined in R_RST_C Reg  above*/

/* The following is for Documentation Only
typedef enum   
{
   ixf6048_eRX_Jn_1_BYTE       = 0,   1 byte 
   ixf6048_eIGNORE_RX_Jn       = 2    Ignore J1 
   ixf6048_eRX_Jn_16_WITH_CRC7 = 4,   16 bytes, starting with CRC7 (SDH) 
   ixf6048_eRX_Jn_64_FREE_FORM = 6,   64 bytes, free form 
   ixf6048_eRX_Jn_64_WITH_LF_CR = 7,  64 bytes with LF,CR at end 
} ixf6048_RxJnFormat_e;  */

/* Rx High Order Path Termination Config */
typedef struct 
{
   ixf6048_HptRdiDetect_e         HptRdiDetect;        /* R_HPT_C1 Bits[15:14]*/
   ixf6048_DetectEnhancedHptRdi_e DetectEnhancedHptRdi;/* R_HPT_C1 Bit 13 */
   ixf6048_HptSlMismatchCnt_e     HptSlMismatchCnt;    /* R_HPT_C1 Bit 12 */
   ixf6048_HpSlmOnC2Config_e      HpSlmOnC2Config;     /* R_HPT_C1 Bit 11*/
   ixf6048_B3CntrCfg_e            B3CntrCfg;           /* R_HPT_C1 Bit 10 */
   ixf6048_HptReiCntrCfg_e        HptReiCntrCfg;       /* R_HPT_C1 Bit 9 */
   ixf6048_Cols30_59_e            Cols30_59;           /* R_HPT_C1 Bit 8 */
   ixf6048_HptRdiOnAtmLcd_e       HptRdiOnAtmLcd;      /* R_HPT_C1 Bit 7 */
   ixf6048_HptRdiOnHptSlm_e       HptRdiOnHptSlm;      /* R_HPT_C1 Bits[6:5]*/

   ixf6048_HptRdiOnJ1Mismatch_e   HptRdiOnJ1Mismatch;  /* R_HPT_C1 Bit 4 */
   ixf6048_HptRdiOnHptUneq_e      HptRdiOnHptUneq;     /* R_HPT_C1 Bit 3 */
   ixf6048_GenHptRdiCfg_e         GenHptRdiCfg;        /* R_HPT_C1 Bits[2:1]*/
   ixf6048_G1SpareBit_e           G1SpareBit;          /* R_HPT_C1 Bit 0 */

   ixf6048_J1Crc7Mismatch_e       J1Crc7Mismatch;     /* R_HPT_C2 Bit 13 */
   ixf6048_J1UnstableMismatch_e   J1UnstableMismatch; /* R_HPT_C2 Bit 12 */
   ixf6048_J1StableCnt_e          J1StableCnt;        /* R_HPT_C2 Bit 11 */
   ixf6048_RxJnFormat_e           ExpectedJ1Format;   /* R_HPT_C2 Bits[10:8]*/
                                 /* R_HPT_C2 Bits[7:6] Unused*/
   ixf6048_RcvHptAisFrc_e         RcvHptAisFrc;      /* R_HPT_C2 Bit 5 */

   ixf6048_AisToHpa_e             RcvHptAisSlmEnbl;  /* R_HPT_C2 Bit 4 */
   ixf6048_AisToHpa_e             RcvHptAisUneqEnbl; /* R_HPT_C2 Bit 3 */
   ixf6048_AisToHpa_e             RcvHptAisTimEnbl;  /* R_HPT_C2 Bit 2 */
                                 /* R_HPT_C2 Bits[1:0] Unused */

   uchar                         ExpectedC2;        /* Expected HPT Signal Label */
   uchar*                        pExpectedJ1String; /* -> J1 string, if used */
                                 /* Driver appends LF,CR or prepends dummy
                                    byte for CRC7, if appropriate */
} ixf6048_RxHptCfg_t;

/***********************************************************************
 *
 * Tx Regenerator Section Termination Configuration - 
 *
 **********************************************************************/

/* Tx RST Scrambling config - T_RMST_OP bit 15 */ 
typedef enum   
{
   ixf6048_eDISABLE_TX_RST_SCRAMBLING=0,   /* Disable Tx RST Scrambling */
   ixf6048_eENABLE_TX_RST_2E7_SCRAMBLING   /* Enable Tx RST Scrambler 2e7 */
} ixf6048_TxRstScrambling_e;

/* Config unused Tx overhead byte values: 0x00, 0xFF
   See: T_RMST_OP bit 14  */
typedef enum   
{
   ixf6048_eUNUSED_TX_OH_ZEROS = 0,   /* Tx 0x00 in unused Overhead bytes */
   ixf6048_eUNUSED_TX_OH_ONES         /* Tx 0xFF in unused Overhead bytes */
} ixf6048_UnusedTxOh_e;

/* Config Tx TZ0 byte value: See T_RMST_OP bits 13:12 */
typedef enum   
{
   ixf6048_eTX_TZ0_USE_ABOVE_DEFAULT = 0,   /* use UnusedTxOh default value */
   ixf6048_eTX_TZ0_IS_AA,                   /* value is 0xAA */
   ixf6048_eTX_TZ0_BY_LINE_SPEED            /* value varies, by Line Speed */
} ixf6048_TxTzo_e;

/* Config Tx SZ0 byte value: See T_RMST_OP bits 11:10 */
typedef enum   
{
   ixf6048_eTX_SZ0_USE_ABOVE_DEFAULT = 0,   /* use UnusedTxOh default value */
   ixf6048_eTX_SZ0_IS_AA,                   /* value is 0xAA */
   ixf6048_eTX_SZ0_BY_LINE_SPEED            /* value varies, by Line Speed */
} ixf6048_TxSzo_e;

/* Config Tx FZ0 byte value: See T_RMST_OP bits 9:8 */
typedef enum   
{
   ixf6048_eTX_FZ0_USE_ABOVE_DEFAULT = 0,   /* use UnusedTxOh default value */
   ixf6048_eTX_FZ0_IS_AA,                   /* value is 0xAA */
   ixf6048_eTX_FZ0_BY_LINE_SPEED            /* value varies, by Line Speed */
} ixf6048_TxFzo_e;

/* PSN_ADDED for B1 Release */
/* T_SC_RSOH Bit[15], T_HPT_C Bit[15] 
	-- ENable the SOH insertion from the TSOH serial input bus channel (cc)
	-- ENable the POH insertion from the TPOH serial input bus channel (cc)*/
typedef enum
{
	ixf6048_eOH_INS_DISABLED =0,
	ixf6048_eOH_INS_ENABLED
}ixf6048_OHInsEna_e;
/* PSN_END B1 Release change */

/* Tx Undefined RSOH Source, except for Row 1,2 National Use
   bytes (ignored if STM-0/STS-1) - 
   See T_SC_RSOH bit 10 */
typedef enum   
{
   ixf6048_eTX_UN_USE_ABOVE_DEFAULT = 0,    /* use UnusedTxOh default value */
   ixf6048_eTX_UN_RX_BYTE                   /* Passed through from Rx Byte */
} ixf6048_TxUnSource_e;

/* Tx Row 1 National Use / Z0 Source (ignored if STM-0/STS-1)
                  - See T_SC_RSOH bit 1 */
typedef enum   
{
   ixf6048_eTX_NU1Z0_FROM_HW = 0,           /* use value from internal h/w */
   ixf6048_eTX_NU1Z0_RX_BYTE                /* Passed through from Rx Byte */
} ixf6048_TxNu1Z0Source_e;

/* Tx D1-D3 Source - See T_SC_RSOH bits 9:8 */
typedef enum   
{
   ixf6048_eTX_D1D3_TRD     = 0, /* From TRD */
   ixf6048_eTX_D1D3_USE_DEFAULT, /* use UnusedTxOh default value */
   ixf6048_eTX_D1D3_RX_BYTE      /* From Rx Byte */
} ixf6048_TxD1D3Source_e;


/* Tx Row 2 National Use Source (ignored if STM-0/STS-1)
   - See T_SC_RSOH bit 7 */
typedef enum   
{
   ixf6048_eTX_NU2_USE_ABOVE_DEFAULT = 0,   /* use UnusedTxOh default value */
   ixf6048_eTX_NU2_RX_BYTE                  /* Passed through from Rx Byte */
} ixf6048_TxNu2Source_e;

/* Tx F1 source - See T_SC_RSOH bits 6:5 */
typedef enum   
{
   ixf6048_eTX_F1_TDOW = 0,        /* From TDOW */
   ixf6048_eTX_F1_USE_DEFAULT =1,     /* use UnusedTxOh default value */
   ixf6048_eTX_F1_RX_BYTE = 2         /* From Rx Byte */
} ixf6048_TxF1Source_e;

/* Tx E1 source - See T_SC_RSOH bits 4:2 */
typedef enum   
{
   ixf6048_eTX_E1_TROW       = 0,  /* From TROW */
   ixf6048_eTX_E1_QUIET_PCM  = 1,  /* Quiet PCM code: 0x7f */
   ixf6048_eTX_E1_USE_DEFAULT= 2,  /* use UnusedTxOh default value */
   ixf6048_eTX_E1_RX_BYTE    = 4   /* From Rx Byte */
} ixf6048_TxE1Source_e;

/* Tx J0 Source - See T_SC_RSOH bit 0 */
typedef enum   
{
   ixf6048_eTX_J0_CPU = 0,               /* From CPU */
   ixf6048_eTX_J0_RX_BYTE                /* From Rx Byte */
} ixf6048_TxJ0Source_e;

/* Configure Tx J0 format - See T_RMST_OP Bits 7:6 */
typedef enum   
{
   ixf6048_eTX_Jn_1_BYTE = 0,    /* 1 byte */
   ixf6048_eTX_Jn_DEFAULT,       /* Default value = 0x01 (former C1 byte) */
   ixf6048_eTX_Jn_16_WITH_CRC7,  /* 16 bytes, starting with CRC7 (SDH) */
   ixf6048_eTX_Jn_64_FREE_FORM   /* 64 bytes, free form */
} ixf6048_TxJnFormat_e;


typedef struct /* Tx Regenerator Section Termination Configuration */
{
   ixf6048_TxRstScrambling_e   TxRstScrambling;  /* T_RMST_OP bit 15 */
   ixf6048_UnusedTxOh_e        UnusedTxOh;       /* T_RMST_OP bit 14 */
   ixf6048_TxTzo_e             TxTzo;            /* T_RMST_OP bits[13:12] */
   ixf6048_TxSzo_e             TxSzo;            /* T_RMST_OP bits[11:10] */
   ixf6048_TxFzo_e             TxFzo;            /* T_RMST_OP bits[9:8] */
   ixf6048_TxJnFormat_e        TxJ0Format;       /* T_RMST_OP bits[7:6] */
                              /* T_RMST_OP bits[5:1] Used for Testing*/

/* PSN_ADDED for B1 Release */
   ixf6048_OHInsEna_e	       TSOHInsEna;	  /* T_SC_RSOH Bit[15] TSOHINS[cc] control input pin enable*/
/* PSN_END B1 Release change */
   ixf6048_TxUnS