ixf6048d.h

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

{
   ixf6048_eTX_CLK_IS_STOPPED = 0,        /* Internally Tied Low*/
   ixf6048_eTX_CLK_IS_RX_SERIAL_CLK,  /* corresponding Rx serial clock input */
   ixf6048_eTX_CLK_IS_TX_CHAN_INPUT_CLK,  /* Its own (per channel) input clock */
   ixf6048_eTX_CLK_IS_TX_COMMON_CLK_INPUT /* The transmit common clock input */
} ixf6048_TxTimingSource_e;

/* Tx TTL Clock config to get TTL Tx output clock - 
         -- Tx Source clock divided by 1,2,..32
         -- See: reg T_COCNF Bits 7:5  */
typedef enum   
{                            /* PSN_DEBUG -- Set to 0 */
   ixf6048_eTX_TTL_CLK_DIV_1 = 0,
   ixf6048_eTX_TTL_CLK_DIV_2,
   ixf6048_eTX_TTL_CLK_DIV_4,
   ixf6048_eTX_TTL_CLK_DIV_8,
   ixf6048_eTX_TTL_CLK_DIV_16,
   ixf6048_eTX_TTL_CLK_DIV_32,
   ixf6048_eTX_TTL_CLK_IS_8_KHZ,      /* Tx output clock is 8 KHz */
   ixf6048_eTX_TTL_CLK_IS_TRISTATED   /* Tx output clock is tristated */
} ixf6048_TxTtlClockDivide_e;

/*------------------ UTOPIA Interface Channel Config --------------------*/

/* Polarity of Rx,Tx parity (even/odd) 
        See Regs: R_UICHCNF, T_UICHNF bit 9 */
typedef enum   
{
   ixf6048_eUTOPIA_ODD_PARITY = 0,
   ixf6048_eUTOPIA_EVEN_PARITY
} ixf6048_UtopiaParity_e;

/* Rx,Tx Decode-response delay config - 
        See Regs: R_UICHCNF, T_UICHNF bit 8 */
typedef enum   
{
   ixf6048_eONE_CYCLE_DECODE_RESPONSE_DELAY = 0,
   ixf6048_eTWO_CYCLE_DECODE_RESPONSE_DELAY
} ixf6048_UtopiaResponseDelay_e;

/* For RXFA & RXPFA polarity config  
    See Reg : R_UICHCNF bit 10 */ 
typedef enum   
{
   ixf6048_eRXFA_ACTIVE_HIGH = 0,     /* High means frame available */
   ixf6048_eRXFA_ACTIVE_LOW           /* Low  means frame available */
} ixf6048_RxFaPolarity_e;

/* For TXPFA, TXSFA, TXFA polarity config  
    See Reg : T_UICHCNF bit 10 */ 
typedef enum   
{
   ixf6048_eTXFA_ACTIVE_HIGH = 0,  /* High means free space avail */
   ixf6048_eTXFA_ACTIVE_LOW        /* Low  means free space avail */
} ixf6048_TxFaPolarity_e;

/*------------------ ATM-specific UTOPIA Channel Configuration -----------*/

/* Note: See cell structures on page .
   Note: HEC is always generated by Amazon chip.
         UTOPIA interface can Rx/Tx 52 bytes (omiting space for HEC byte)
         or pass another 8/16/32-bit (dummy) word where HEC byte would be. */

/* ATM Cell Data Cfg -- RXENB is only taken into account at the beginning 
         of the cell */
typedef enum
{
   ixf6048_eCELL_BURST_NORMAL_MODE =0,
   ixf6048_eCELL_BURST_PASS_THROUGH_MODE
} ixf6048_CellBurstCnf_e;
/* ATM Cell data structure - pass null HEC word or not
        See Regs: R_UICHCNF, T_UICHCNF bit 6 */
typedef enum   
{
   ixf6048_ePASS_NULL_HEC_WORD = 0,  /* Rx/Tx dummy word for HEC byte */
   ixf6048_eDO_NOT_PASS_HEC          /* No Rx/Tx dummy word for HEC byte */
} ixf6048_DummyHecWord_e;

/* Note:

   RxCellAvailDeassertByteNum configures when the "Cell Available in FIFO to
   send to UTOPIA" signals are deasserted, so the ATM Layer device can know
   that the current ATM cell is the last ATM cell in the FIFO. Namely, the
   value specifies the ATM payload byte number (1-48), after which the
   "Cell Available" signals will be deasserted, on the next RXCLK rising edge
   after the word containing the specified ATM payload byte.
   See also Reg R_UICHCNF bits 5:0

   TxCellAvailDeassertByteNum configures when the "Space Available in FIFO to
   hold cell from UTOPIA" signals are deasserted, so the ATM Layer device can
   know that the current ATM cell is the last ATM cell to be sent to the FIFO,
   for now. Namely, the value specifies the ATM payload byte number (9-48),
   after which the "Space Available" signals will be deasserted, on the next
   TXCLK rising edge after the word containing the specified ATM payload byte.
   See also  Reg T_UICHCNF bits 5:0 XmtCADeassert

   TxFifoDepth configures the depth of the Tx FIFO, in cells. Namely, for
   Channel 0 (1-64 cells) and for Channels 1-3 (1-16 cells).
   After the Tx FIFO contains TxFifoDepth number of cells, the "Space
   Available" signal (TXFA) is deasserted. This is available to be able to
   reduce the cell delay, by limiting the Tx FIFO depth.
   See also Reg T_UIFDP bits 6:0 XmtFDCnf
*/
typedef struct /* ATM-specific Channel config */
{
   ixf6048_CellBurstCnf_e   RxCellBurstCnf; 
   ixf6048_CellBurstCnf_e   TxCellBurstCnf; 
   
   ixf6048_DummyHecWord_e   RxDummyHecWord;
   ixf6048_DummyHecWord_e   TxDummyHecWord;

   uchar                   RxCellAvailDeassertByteNum;
   uchar                   TxCellAvailDeassertByteNum;

   uchar                   TxFifoDepth;

} ixf6048_UtopiaAtmChanCfg_t;

/*------------------ POS-specific UTOPIA Channel Configuration -----------*/
/***********************************************************************
 * Data to configure programmable POS watermarks
 *
 * Notes:
 *    RcvPWM -- configures when the "POS Data Available" signal
 *    (RXFA) is asserted and deasserted.
 *    Data Available when Rx FIFO contains an End of Packet, or at least
 *    BytesAvailForDataAvail number of bytes.
 *    Data Not Available when Rx FIFO does not contain an End of Packet and
 *    fewer bytes available than that specified by RcvPWM.
 *    See also R_PWM 11:0.
 *
 *    RxFaDeassertOnLow -- specifies whether Data Available signal asserted
 *    only when FIFO contains BytesAvailForDataAvail number of bytes,
 *    ignoring presence of End of Packet.
 *    See also R_UICNF bit 6.
 *
 *    XmtNFPWM -- configures when the "Free Space Available in the Tx FIFO"
 *    signals (TXFA etc.) are asserted and deasserted, as follows.
 *    See also T_NFPWM & T_NEPWM 9:0 for XmtNFPWM & XmtNEPWM
 *
 *    "Space Available" asserted -- when the Tx FIFO has free at least
 *    XmtNFPWM number of bytes.
 *
 *    "Space Available" deasserted -- when the Tx FIFO has fewer than
 *    XmtNEPWM  number of bytes free.
 *
 *    Num Bytes quantized by Driver to 4,8,12,...Max
 *    BytesAvailForDataAvail Range: Chan 1-3: 4-1024, Chan 0: 4-4096
 *    xxxSpaceAvail Range: Chan 1-3: 4-256,  Chan 0: 4-1024
 *    Note: Num Bytes converted to num 4-byte words for hardware.
 **********************************************************************/
/* To configure values of POS watermarks */ 
typedef struct 
{
   ushort    RcvPWM;   /* Rx Pos Watermark */
   ushort    XmtNFPWM; /* Tx Near Full WM  */
   ushort    XmtNEPWM; /* Tx Near Empty WM */
} ixf6048_PosWatermarks_t;

/* Channel Interface Config */ 
typedef struct 
{
   
   ixf6048_LineSideSpeed_e        LineSideSpeed;
   ixf6048_RcvLockConfig_e        RcvLockConfig;
   
   ixf6048_RxLineSideInterface_e  RxLineSideInterface;
   ixf6048_RxTtlClockDivide_e     RxTtlClockDivide;

   ixf6048_XmtPClkOutConfig_e     XmtPClkOutConfig;
   ixf6048_TxLineSideInterface_e  TxLineSideInterface;
   ixf6048_TxTimingSource_e       TxTimingSource;
   ixf6048_TxTtlClockDivide_e     TxTtlClockDivide;

   ixf6048_UtopiaParity_e         RxUtopiaParity;
   ixf6048_UtopiaParity_e         TxUtopiaParity;

   ixf6048_UtopiaResponseDelay_e  RxUtopiaResponseDelay;
   ixf6048_UtopiaResponseDelay_e  TxUtopiaResponseDelay;

   ixf6048_RxFaPolarity_e         RxFaPolarity;
   ixf6048_TxFaPolarity_e         TxFaPolarity;

                    /* Config(s) below can be 0'ed out if not needed */
   ixf6048_UtopiaAtmChanCfg_t  UtopiaAtmChanCfg; /* Ignored if not ATM */
   ixf6048_PosWatermarks_t     PosWatermarks;    /* Ignored if not POS */

} ixf6048_ChanIfCfg_t;

/***********************************************************************
 * Rx Regenerator Section Termination Configuration - Pg 198 on
 **********************************************************************/

/* Rx RST Descrambling config - 
        See: Reg R_RSTC bit 15 */ 
typedef enum   
{
   ixf6048_eDISABLE_RX_RST_DESCRAMBLING=0,     /* Disable Rx RST Descrambling */
   ixf6048_eENABLE_RX_RST_2E7_DESCRAMBLING     /* Enable Rx RST Descrambling 2e7 */
} ixf6048_RxRstScrmblCnfg_e;

/* Use external frame pulse reference input (RFPI), or not  
        See: Reg R_RSTC bit 14 */ 
typedef enum   
{
   ixf6048_eRX_RST_IGNORE_RFPI=0,     /* Ignore RFPI - enable internal alignment */
   ixf6048_eRX_RST_USE_RFPI           /* Use    RFPI - disable internal alignment */
} ixf6048_RxRstFBaDsbl_e;

/* Config of Frame Work Checking during Frame desynchronization
        -- Only Valid for OC12 and OC48.
        See: Reg R_RSTC bit 13, 12 */ 
typedef enum   
{
   ixf6048_eFWD_OFF_CNFG_LONG_FORMAT = 0, /* 24 Bytes for OC-48, Entire Frame for OC-12*/
   ixf6048_eFWD_OFF_CNFG_SHORT_FORMAT     /* 6 bytes for OC-48 and OC-12 */
} ixf6048_RstRcvFwdCnfg_e;


/* B1 error counter counts Bit or Block errors
        See: Reg R_RSTC bit 11 */ 
typedef enum
{
   ixf6048_eCOUNT_B1_BIT_ERRORS = 0,  /* Count B1 bit errors */
   ixf6048_eCOUNT_B1_BLOCK_ERRORS     /* Count B1 block errors */
} ixf6048_B1CntrCfg_e;

/* Config Loss of Signal Detection -
        See: Reg R_RSTC bit 10:9 */ 
typedef enum   
{
   ixf6048_eRX_RST_LOS_ON_20US_ZEROS = 0,/* LOS = 20 Microsecs of 0's */
   ixf6048_eRX_RST_LOS_ON_20US_LOS,      /* LOS = 20 Microsecs of no change */
   ixf6048_eRX_RST_LOS_ON_25US_ZEROS,    /* LOS = 25 Microsecs of 0's */
   ixf6048_eRX_RST_LOS_ON_25US_LOS       /* LOS = 25 Microsecs of no change */
} ixf6048_RxRstLos_e;


/* Enable/Disable Blue Clock on Loss of Signal or Clock  
        See: Reg R_RSTC bit 8 */ 
typedef enum   
{
   ixf6048_eDISABLE_BLUE_CLOCK_ON_LOS_LOC=0,
   ixf6048_eENABLE_BLUE_CLOCK_ON_LOS_LOC
} ixf6048_BlueClkOnLosLoc_e;

/* Enable/Disable AIS Gen from RST to MST on Loss of Frame
        See: Reg R_RSTC bit 7 */ 
typedef enum   
{
   ixf6048_eDISABLE_RX_RST_AIS_ON_LOF=0,
   ixf6048_eENABLE_RX_RST_AIS_ON_LOF
} ixf6048_RxRstAisOnLof_e;

/* Enable/Disable AIS Gen from RST to MST on Loss of Signal
        See: Reg R_RSTC bit 6 */ 
typedef enum   
{
   ixf6048_eDISABLE_RX_RST_AIS_ON_LOS=0,
   ixf6048_eENABLE_RX_RST_AIS_ON_LOS
} ixf6048_RxRstAisOnLos_e;

/* Enable/Disable AIS Gen from RST to MST on Loss of Clock
        See: Reg R_RSTC bit 5 */ 
typedef enum   
{
   ixf6048_eDISABLE_RX_RST_AIS_ON_LOC =0,
   ixf6048_eENABLE_RX_RST_AIS_ON_LOC
} ixf6048_RxRstAisOnLoc_e;

/* Enable/Disable AIS Gen from RST to MST on J0 mismatch
        See: Reg R_RSTC bit 3 */ 
typedef enum   
{
   ixf6048_eDISABLE_RX_RST_AIS_ON_J0=0,
   ixf6048_eENABLE_RX_RST_AIS_ON_J0
} ixf6048_RxRstAisOnJ0_e;


/* Configure Loss of Clock Alarm Filtering
        See: Reg R_RSTC bits 2:1 */ 
typedef enum
{
   ixf6048_eNO_LOC_FILTERING = 0,
   ixf6048_eWEAK_LOC_FILTERING = 2,
   ixf6048_eSTRONG_LOC_FILTERING = 3
} ixf6048_RxRstLocFiltering_e;

/* STM-0/STS-1 NDF Frame Acquisition config (else Normal)
        See: Reg R_RSTC bit 0 */ 
typedef enum   
{
   ixf6048_eSTM0_NDF_NORMAL_FRAME_ACQUISITION = 1,
   ixf6048_eSTM0_NDF_ROBUST_FRAME_ACQUISITION
} ixf6048_NdfFrameAcqCfg_e;

/* Out of Frame Configuration    LOF_LMN Bit 15
      -- Num consectutive eroneous frame words to detect 
         before going to an Out of Frame Condition */
typedef enum
{
   ixf6048_eOOF_CNFG_4_FRAMES = 0, /* Declare OOF within 500 uS */
   ixf6048_eOOF_CNFG_5_FRAMES      /* Declare OOF within 625 uS */
}ixf6048_RcvOofCnfg_e;

/* Loss of Frame State Machine Parameters 
    See Reg LOF_LMN         */
typedef struct 
{
   uchar L; /* 1-32 = num non-consecutive frames with OOF to enter LOF state */
   uchar M; /* 1-32 = num consecutive frames with no OOF to reenter Normal */
   uchar N; /* 1-32 = num consecutive frames with no OOF to reenter Normal
                      state, from LOF state */
} ixf6048_LofStateMachineParms_t;

/* Configure whether J0 CRC7 error masks J0 Mismatch
        See: reg J0_RSTC bit 5 */
typedef enum   
{
   ixf6048_eJ0_CRC7_MASKS_MISMATCH = 0,       /*CRC7 error masks Mismatch error */
   ixf6048_eJ0_CRC7_AND_MISMATCH_INDEPENDANT  /* CRC7 and Mismatch error are separate */
} ixf6048_J0Crc7Mismatch_e;

/* Configure whether J0 Unstable sets J0 Mismatch
        See: reg J0_RSTC bit 4 */
typedef enum
{
   ixf6048_eJ0_UNSTABLE_SETS_MISMATCH = 0,       /* J0 Unstable sets J0 Mismatch */
   ixf6048_eJ0_UNSTABLE_AND_MISMATCH_INDEPENDANT /* J0 Unstable & Mismatch separate */
} ixf6048_J0UnstableMismatch_e;