📄 ixf6048d.h
字号:
ixf6048_ePARITY_PROTECTS_PARALLEL_DATA_BUS_ONLY =0,
ixf6048_ePARITY_PROTECTS_PARALLEL_DATA_BUS_AND_FRAME_PULSE
} ixf6048_ParityModeConfig_e;
/* Rx/Tx Mode Configuration
-- LPSCNF Bit 1 and Bit 0 */
typedef enum
{
ixf6048_eODD_PARITY = 0,
ixf6048_eEVEN_PARITY
} ixf6048_ParityConfig_e;
/* Line side Parity Configuration
- Reg LSPCNF */
typedef struct
{
ixf6048_ParityModeConfig_e PrtyModeConfig;
ixf6048_ParityConfig_e RxParityConfig;
ixf6048_ParityConfig_e TxParityConfig;
} ixf6048_LineSideParityConfig_t;
/* Non Concatenated Mode config Register
See Reg NCMODECNF Bits 0, 2, 4*/
typedef struct
{
ixf6048_J0MuxConfig_e J0MuxConfig;
ixf6048_MuxDemuxConfig_e BWMuxConfig;
ixf6048_MuxDemuxConfig_e BWDeMuxConfig;
} ixf6048_NonConcatModeCnfg_t;
/*------------------ POS-specific UTOPIA Config ----------------------------*/
/* PSN_ADDED for B1 Release */
/* R_UICNF Bit[11] Pos Mode Only
-- Block Reads on EOF, or if FIFO is Empty
-- Receive side only */
typedef enum
{
ixf6048_eRCV_VAL2_CNF_READ_BLOCKED_IF_EOF_OR_FIFO_EMPTY =0,
ixf6048_eRCV_VAL2_CNF_READ_BLOCKED_IF_EOF_ONLY
}ixf6048_RcvVal2Cnf_e;
/* PSN_END B1 RElease Changes */
/* POS-UTOPIA Config - Regs R_UICNF, T_UICNF bit 0.
(used for Rx & Tx interface).
If like ATM interface, has data transfer and port selection
processes running in parallel.
If memory mapped, there is no selection cycle or FIFO status
polling, just port addressing. */
typedef enum
{
ixf6048_ePOS_UTOPIA_LIKE_ATM = 0,
ixf6048_ePOS_UTOPIA_MEMORY_MAPPED
} ixf6048_PosUtopiaSelMode_e;
/* RXFA,TXFA Status config - Regs R_UICNF, T_UICNF bit 5
namely: Direct Status Indication mode, or
Multiplexed Status Polling */
typedef enum
{
ixf6048_eFA_MULTIPLEXED_STATUS_POLLING=0,
ixf6048_eFA_DIRECT_STATUS_INDICATION
} ixf6048_FaStatus_e;
/* RXVAL config for POS mode - Reg R_UICNF bit 7
Note: Configures whether RXVAL is deasserted only when
reading an empty FIFO, or also at end of each packet.
Note: This would be useful to provide time for an attached
packet switch to switch buffers, in between packets. */
typedef enum
{
ixf6048_eRXVAL_DEASSERT_ON_FIFO_EMPTY=0,
ixf6048_eRXVAL_DEASSERT_ON_EOP
} ixf6048_RxValDeassertAtEop_e;
/* RXFA config for POS mode - Reg R_UICNF bit 6
Note: Configures how the RXFA (Frame Available) signal is
deasserted when there are fewer words in the FIFO than
specified by the Rx Programmable Watermark
(BytesAvailForDataAvail in UtopiaPosChanCfg).
Namely, if Frame Available is deasserted even if EOF present,
or only when EOF not present. */
typedef enum
{
ixf6048_eRXFA_DEASSERT_ON_LOW_IF_NO_EOF=0,
ixf6048_eRXFA_DEASSERT_ON_LOW_ALWAYS
} ixf6048_RxFaDeassertOnLow_e;
/* Config for POS mode - Reg T_UICNF bit 6
Note: When 0, The POS xmitter will start the Transmission
of a new packet if the FIFO contains an EOF OR the FIFO contains
a number of words equal or greater than the Transmit initiation
Min level (Reg T_UIIML)*/
typedef enum
{
ixf6048_eTX_AT_EOF_OR_GT_MIN_LEVEL = 1,
ixf6048_eTX_AT_GT_MIN_LEVEL_ONLY
} ixf6048_TxEofEmpty_e;
/* ----------------------------------------------------------------------
Notes for Utopia-specific Chip Configuration:
This Structure contains the Chip-Level Utopia Configuration that are
common to all 4 channels. This is divided into the Transmit and receive
Sides.
---------------------------------------------------------------------- */
typedef struct /* Utopia-specific Chip Configuration */
{
/* Rx Side Config */
/* PSN_ADDED B1 Release Updates */
ixf6048_UOutEnCnf_e RcvUOutEnCnf; /* GOCNF Bit[11] RcvUOutEnCnf B1 Release*/
/* PSN_END Added Bits */
ixf6048_UtopiaInterface_e RxUtopiaInterface; /* R_UICNF Bit 3, GOCNF Bit[7] */
ixf6048_RcvAtmHecConfig_e RcvAtmHecConfig; /* R_UICNF Bit 10 - Only Valid in
8 Bit Mode (RcvUWidth ='00') */
ixf6048_UtopiaSmallMemCfg_e RxUtopiaSmallMemCfg; /* R_UICNF Bit 9 */
ixf6048_UtopiaMultiPhy_e RxUtopiaMultiPhy; /* R_UICNF Bit 5 */
ixf6048_MPhyDevCnf_e RcvMPhyDevCnf; /* R_UICNF Bit 4 */
ixf6048_UnusedUtopiaPinsImp_e UnusedUtopiaPinsImp;
/* Tx Side Config */
/* PSN_ADDED B1 Release Updates */
ixf6048_UOutEnCnf_e XmtUOutEnCnf; /* GOCNF Bit[10] XmtUOutEnCnf B1 Release*/
/* PSN_END Added Bits */
ixf6048_UtopiaInterface_e TxUtopiaInterface; /* T_UICNF Bit 3 */
ixf6048_UtopiaSmallMemCfg_e TxUtopiaSmallMemCfg; /* T_UICNF Bit 7 */
ixf6048_UtopiaMultiPhy_e TxUtopiaMultiPhy; /* T_UICNF Bit 5 */
ixf6048_MPhyDevCnf_e XmtMPhyDevCnf; /* T_UICNF Bit 4 */
/* Common Setup */
uchar UtopiaDevBaseAddress; /* GOCNF Bits[2:0] */
}ixf6048_UtopiaChipCfg_t;
/* ----------------------------------------------------------------------
Notes for POS-specific Chip configuration below:
The Pos specific Config describes the behaviour of the Utopia interface
when in POS mode.
RxFifoRestartLevel: defines number of words in the Rx FIFO to restart
accepting packets after an Rx FIFO overflow. See also reg R_UIIML bits 7:1.
TxFifoRestartLevel: defines number of words in the Tx FIFO to restart
transmitting packets, after a Tx FIFO underflow. See also Reg T_UIIML bits 7:1.
For Rx/TxFifoRestartLevel:
For Quad mode: for channels 0-3, user's value is quantized to (16N +1)
where N = 0..15; i.e. quantized value is 1,17,33, ... 241
For Single Channel mode: For channel 0, user's value is quantized to
(16N + 1), where N = 0..63, i.e. quantized value
is 1,17,33, ... 1009
---------------------------------------------------------------------- */
typedef struct /* POS-specific Chip configuration */
{
/* Rx side Cfg */
ixf6048_PosUtopiaSelMode_e RxPosUtopiaSelMode; /* For Rx */
ixf6048_FaStatus_e RxFaStatus; /* For Rx */
ixf6048_RxValDeassertAtEop_e RxValDeassertAtEop;
ixf6048_RxFaDeassertOnLow_e RxFaDeassertOnLow;
ushort RxFifoRestartLevel; /* See above */
/* PSN_ADDED for B1 Release */
ixf6048_RcvVal2Cnf_e RxVal2Cnf; /* R_UICNF Bit[11] Rx Mode Only */
/* PSN_END B1 RElease Changes */
/* Transmit Cfg */
ixf6048_PosUtopiaSelMode_e TxPosUtopiaSelMode; /* For Tx */
ixf6048_FaStatus_e TxFaStatus; /* For Tx */
ixf6048_TxEofEmpty_e TxEofEmpty;
ushort TxFifoRestartLevel; /* See above */
} ixf6048_PosChipCfg_t;
/* ----------------------------------------------------------------------
Notes for Chip configuration below:
UtopiaDevBaseAddress: 3-bit base address of UTOPIA device, in the UTOPIA
interface. Compared to RXADDR[4:2] and TXADDR[4:2]. See Reg GOCNF 2:0
---------------------------------------------------------------------- */
typedef struct /* Amazon Chip configuration */
{
ixf6048_ByteChgUpdDsbl_e ByteChgUpdDsbl; /* Enables/Disables Receive byte Updates
when a Register's byte Change interupt
is Active -- See Reg MACNF - Bit2 */
/* PSN_ADDED B1 Release Following Config Bits */
ixf6048_GenIOVal_e GenIOVal; /* GOCNF Bit[13] */
ixf6048_GenIOMode_e GenIOMode; /* GOCNF Bit[12] */
ixf6048_PeclMsbCnf_e XmtPeclMsbCnf; /* XMT PECL MSB Config GOCNF Bit[9] */
ixf6048_PeclMsbCnf_e RcvPeclMsbCnf; /* Rcv PECL MSB Config GOCNF Bit[8] */
/* PSN_END End Of Added Bits for B2 Release */
ixf6048_UtopiaChipCfg_t UtopiaChipCfg; /* Utopia Interface Configuration */
ixf6048_OrderWirePulseByteLocn_e OrderWirePulseByteLocn; /* see Above -- OHPCNF*/
ixf6048_OverheadPortMode_e OverheadPortMode;
uchar RxFramePulseByteNum; /* R_FPCNF 7:0 */
uchar TxFramePulseOutByteNum; /* T_FPCNF 15:8 */
uchar TxFramePulseInByteNum; /* T_FPCNF 7:0 */
ixf6048_OutClockPolarity_e OutClockPolarity; /* OCPCNF */
ixf6048_InClockPolarity1_e InClockPolarity1; /* ICPCNF1 */
ixf6048_InClockPolarity2_e InClockPolarity2; /* ICPCNF2 */
ixf6048_NonConcatModeCnfg_t NonconcatModeCnfg; /* NCMODECNF */
ixf6048_LineSideParityConfig_t LineSideParityConfig; /* LSPCNF */
ixf6048_PosChipCfg_t PosChipCfg; /* {0} if no POS chans */
} ixf6048_ChipLevelCfg_t;
/***********************************************************************
* Channel Interface Configuration structures - for Channels 0-3
*
* Note: For Single channel interface, only Channel 0 may be configured.
*
* Note: To support the interfacing of dissimilar Line Side interfaces
* (including between SONET and SDH) in a Repeater or Transparent
* channel configuration, the Rx and Tx Line Side interfaces are
* specified indepently.
* When configured as an ATM or POS channel, warnings are issued if
* the Rx and Tx Line Side interfaces are different, but the
* configuration is accepted as specified.
*
* The Rx and Tx sides of the UTOPIA interface are specified to the
* Driver as a unit, and the Driver configures both sides of the
* UTOPIA hardware interface in the same way.
**********************************************************************/
/*------------------ SONET/SDH Line Side Channel Config -----------------*/
/* SONET/SDH Line Side Speed - See compatability table Pg 10
See also:
Reg GOCNF bits 6:5;
Reg COCNF bits 1:0, */
typedef enum
{
ixf6048_eSINGLE_STS_48C = 1, /* Single STS-48c */
ixf6048_eSINGLE_STM_16C, /* Single STM-16c */
/* = ixf6048_eSINGLE_STS_48C, */
ixf6048_eSINGLE_STS_48, /* Single STS-48 */
ixf6048_eSINGLE_STM_16, /* Single STM-16 */
/* = ixf6048_eSINGLE_STS_48, */
ixf6048_eSINGLE_STS_12, /* Single STS-12 */
ixf6048_eSINGLE_STM_4, /* Single STM-4 */
/* = ixf6048_eSINGLE_STS_12, */
ixf6048_eSINGLE_STS_12C, /* Single STS-12c */
ixf6048_eSINGLE_STS_3C, /* Single STS-3c */
ixf6048_eSINGLE_STS_3, /* Single STS-3 */
ixf6048_eQUAD_STS_12C, /* Quad STS-12c */
ixf6048_eQUAD_STM_4C, /* Quad STM-4c */
/* = ixf6048_eQUAD_STS_12C, */
ixf6048_eQUAD_STS_3C, /* Quad STS-3c */
ixf6048_eQUAD_STM_1, /* Quad STM-1 */
/* = ixf6048_eQUAD_STS_3C, */
ixf6048_eQUAD_STS_1 /* Quad STS-1 */
} ixf6048_LineSideSpeed_e;
/* Rx Line Side Interface - See compatability table Pg 10
See R_COCNF Bits 4:2
Note: 32-bit TTL and 16-bit or 8-bit PECL only valid for
Single Channel line interface. */
typedef enum
{
ixf6048_eRX_32_BIT_TTL=0x0, /* 32-bit TTL -- Single Mode Only*/
ixf6048_eRX_8_BIT_TTL =0x2, /* 8-bit TTL */
ixf6048_eRX_1_BIT_TTL =0x3, /* 1-bit TTL */
ixf6048_eRX_16_BIT_PECL=0x4, /* 16-bit PECL -- Single Mode Only*/
ixf6048_eRX_8_BIT_PECL =0x5, /* 8-bit PECL -- Single Mode Only*/
ixf6048_eRX_1_BIT_PECL =0x7 /* 1-bit PECL */
} ixf6048_RxLineSideInterface_e;
/* Rx TTL Clock config to get TTL Rx output clock -
-- Rx Input clock divided by 1,2,..32
-- See: R_COCNF, T_COCNF Bits 7:5 */
typedef enum
{
ixf6048_eRX_TTL_CLK_DIV_1 = 1,
ixf6048_eRX_TTL_CLK_DIV_2,
ixf6048_eRX_TTL_CLK_DIV_4,
ixf6048_eRX_TTL_CLK_DIV_8,
ixf6048_eRX_TTL_CLK_DIV_16,
ixf6048_eRX_TTL_CLK_DIV_32,
ixf6048_eRX_TTL_CLK_IS_8_KHZ, /* Rx output clock is 8 KHz */
ixf6048_eRX_TTL_CLK_IS_TRISTATED /* Rx output clock is tristated */
} ixf6048_RxTtlClockDivide_e;
/* Receive LOCK Config:
-- Configures how the input pins RLOCK_i (i=0,1,2,3) are used to
switch the internal Receive Cloick Reference to the Blue Clock.
-- R_COCNF Bit 8*/
typedef enum
{
ixf6048_eSWITCH_TO_BLUE_CLOCK_ON_ACTIVE_HIGH=0, /* Switch when RLOCK_i=1 */
ixf6048_eSWITCH_TO_BLUE_CLOCK_ON_ACTIVE_LOW /* Switch when RLOCK_i=0 */
} ixf6048_RcvLockConfig_e;
/* Tx Line Side Interface - See compatability table Pg 10
See:Reg T_COCNF 4:2
Note: 32-bit TTL and 16-bit or 8-bit PECL only valid for
Single Channel line interface.*/
typedef enum
{
ixf6048_eTX_32_BIT_TTL=0x0, /* 32-bit TTL -- Single Mode Only*/
ixf6048_eTX_8_BIT_TTL =0x2, /* 8-bit TTL */
ixf6048_eTX_1_BIT_TTL =0x3, /* 1-bit TTL */
ixf6048_eTX_16_BIT_PECL=0x4, /* 16-bit PECL -- Single Mode Only*/
ixf6048_eTX_8_BIT_PECL =0x5, /* 8-bit PECL -- Single Mode Only*/
ixf6048_eTX_1_BIT_PECL =0x7 /* 1-bit PECL */
} ixf6048_TxLineSideInterface_e;
/* Operation of the PECL Output Clock
-- T_COCNF Bit 10 */
typedef enum
{
ixf6048_eXMT_PECL_CLK_ENABLED = 0,
ixf6048_eXMT_PECL_CLK_DISABLED /* PECL Output Clock in High Impedence */
} ixf6048_XmtPClkOutConfig_e;
/* Tx Timing Source config -- Transmitter is clock
- T_COCNF 9:8 */
typedef enum
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -