ixf6048d.h

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/*
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2001 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *   AUTHOR:         $Author: lagarwal $
 *   DATE:           $Date: 2002/11/15 17:51:11 $
 *   LAST MODIFIED:  $Modtime: 5/17/02 1:58p $
 *   REV#:           $Revision: 1.1.1.1 $
 *   LOGFILE:        $Logfile: /Embedded/source/drivers/ixf/ixf6048/ixf6048d.h $
 *   WORKFILE:       $Workfile: ixf6048d.h $
 *
 * --------------------------------------------------------------------------
 * Project: IXF6048
 *
 * Purpose: Provides the data structures for Ixf6048
 *			
 * Notes:
 *    This File is used to Generate Source Code and therefore the 
 *    following Rules MUST be followed when defining enums and Structures:
 *
 *    Enums:
 *   
 *    typedef enum                  Must be Line 1 
 *    {                             Open Bracket On a Line by itself -- Comments NOT allowed
 *          TheFirstEnum = 0,       = 0,1... is optional, and comments are OK
 *          ThenNextEnum,           Comma delineates the values
 *             ...
 *          TheLastEnumValue        The LastLine Comma is optional
 *    } TheEnumName;                TheName MUST be on the Same Line as Close Parenthesis
 *	  -- Comments MUST NOT On the Open Parenthesis line!
 *    -- Comments may traverse multiple lines!
 *    -- Blank Lines Are Allowed
 *    -- The Open and Close Parentheses MUST be in the First Position on the Line.
 *			
 * --------------------------------------------------------------------------
 * CompilerFlags: 
 * --------------------------------------------------------------------------
 * --------------------------------------------------------------------------
 *   $Log: ixf6048d.h,v $
 *   Revision 1.1.1.1  2002/11/15 17:51:11  lagarwal
 *   rename dir
 *
 *   Revision 1.4  2002/10/31 19:03:23  machambe
 *   no message
 *
 *   Revision 1.2  2002/10/27 18:21:36  machambe
 *   no message
 *
 *   Revision 1.2  2002/10/14 09:41:20  machambe
 *   no message
 */ 

#ifndef BB6048D_H_ /* Include file contents only once per compilation */
#define BB6048D_H_

/***********************************************************************/
#ifdef AMAZON_BORLAND_UI
#include "bb_util.h"               //LC -1/3/02/ -needed to include this file
#include "oht_data.h"
#endif
/************************************************************************/
                          
/* Global Constants */
#define MAX_NUM_CHANNELS 4

/***********************************************************************
 * Chip Configuration structures
 **********************************************************************/
/* PSN_  -- Comment Added Here
	MACNF Bit[2]
*/
typedef enum
{
   ixf6048_eBYTE_CHG_UPDATE_ENABLE = 0,
   ixf6048_eBYTE_CHG_UPDATE_DISABLE
}ixf6048_ByteChgUpdDsbl_e;

/* PSN_ADDED B1 Release Updates
----------- GOCNF Config Bits For B2 Release ----------------*/
/* GOCNF Bit[13] */
typedef enum
{
	ixf6048_eGEN_IO_VAL_LOW = 0,
	ixf6048_eGEN_IO_VAL_HIGH
}ixf6048_GenIOVal_e;

/* GOCNF Bit[12] */
typedef enum
{
	ixf6048_eGEN_IO_MODE_INPUT = 0,
	ixf6048_eGEN_IO_MODE_OUTPUT
}ixf6048_GenIOMode_e;

/* GOCNF Bit[9] GOCNF Bit[8]
	 XMT and RCV PECL MSB Config */
typedef enum
{
	ixf6048_ePECL_MSB_CNF_BIT_PN_15 =0,
	ixf6048_ePECL_MSB_CNF_BIT_PN_0
}ixf6048_PeclMsbCnf_e;

/* PSN_END Added Bits */
/*------------------ UTOPIA Config -----------------------------------*/
/* PSN_ADDED B1 Release Updates
----------- GOCNF Config Bits For B2 Release ----------------*/
/* GOCNF Bit[11] GOCNF Bit[10]
	XmtUOutEnCnf and RcvUOutEnCnf */
typedef enum
{
	ixf6048_eUTOPIA_OUT_EN_CNF_TRISTATE_IF_UOEN_EQ_0 = 0,
	ixf6048_eUTOPIA_OUT_EN_CNF_NOT_DISABLED_INDEPENDANTLY
}ixf6048_UOutEnCnf_e;
/* PSN_END Added Bits */

/* UTOPIA interface - See compatability table Pg 10
         Note: Used for Rx and Tx UTOPIA interface
         See reg  GOCNF Bit 7 for U64Mode
         See regs R_COCNF Bits[4:2], 
                  T_COCNF Bits[4:2]
         and R_UICNF, T_UICNF      */
typedef enum 
{
   ixf6048_eUTOPIA_L3_64_BIT_USING_TTL_PINS = 1,/* U64Mode = 0 */
   ixf6048_eUTOPIA_L3_64_BIT_USING_SOH_PINS,    /* U64Mode = 1 */
                                 /* Level 3 with 64-bit data bus, using either
                                    SOH or TTL pins, for extra UTOPIA pins */
   ixf6048_eUTOPIA_L3_32_BIT,      /* Level 3 with 32-bit data bus */
   ixf6048_eUTOPIA_L3_4_X_8_BIT,   /* Level 3 with 4 independent 8-bit buses */
   ixf6048_eUTOPIA_L2_16_BIT,      /* Level 2 with 16-bit data bus */
   ixf6048_eUTOPIA_L2_4_X_16_BIT,  /* Level 2 with 4 independant 16-bit data buses */
   ixf6048_eUTOPIA_L2_4_X_8_BIT,   /* Level 2 with 4 independant 8-bit data buses */
   ixf6048_eUTOPIA_L2_8_BIT,       /* Level 2 with 8-bit data bus */
   ixf6048_eUTOPIA_L1_4_X_8_BIT    /* Level 1 with 4 independent 8-bit buses */

} ixf6048_UtopiaInterface_e;

/* Single/Multiple Devices on PHY - Regs R_UICNF, T_UICNF bit 3
      Note:
         o  For Single   UTOPIA config - RXFA, TXFA always driven.
         o  For Multiple UTOPIA config - RXFA, TXFA only driven
            when RXADDR, TXADDR  matches the device address.
         o  For Multi-PHY  h/w config - must use MULTIPLE spec
         o  For Single-PHY h/w config - can use either spec. */
typedef enum
{
   ixf6048_eSINGLE_UTOPIA_DEV = 0,    /* Single UTOPIA device on PHY */
   ixf6048_eMULTIPLE_UTOPIA_DEVS      /* Multiple UTOPIA devices on PHY */
} ixf6048_UtopiaMultiPhy_e;

/* Configuration of the Receive interface as follows 
      -- When Amazon-A Shares the Rx interface, The Rx outputs MUST only be 
         driven when Selected. 
      -- When Amazon-a is the only device, then the output CAN be always be driven.
      -- R_UICNF, T_UICNF Bit 4 */
            
typedef enum
{
   ixf6048_eOUTPUT_ALWAYS_DRIVEN = 0,        /* CAN be used when Single device */
   ixf6048_eOUTPUT_ONLY_DRIVEN_WHEN_SELECTED /* MUST be used when Interface is Shared */
} ixf6048_MPhyDevCnf_e;


/* Config for the Extra HEC byte when in 8-Bit mode -- Reg R_UICNF Bit10 */
typedef enum
{
   ixf6048_eEXTRA_BYTE_IS_RX_BYTE = 0,  /* The Received HEC is passed as the Extra Byte */
   ixf6048_eEXTRA_BYTE_IS_STATUS,       /* 2 Status Bits are passed -- Bit0 and Bit 1*/
   ixf6048_eNOT_IN_8_BIT_MODE           /* This bit is ignored -- Place holder only */
}ixf6048_RcvAtmHecConfig_e;

/* Config to reduce the size of the Rx/Tx UTOPIA FIFO memory used by Channel 0
         -- R_UICNF Bit 9, T_UICNF Bit 7 */
typedef enum
{
   ixf6048_eSMALL_MEM_CHAN_0_FIFO_16K=0, /* Chan 0 Fifo is 16k Bytes */
   ixf6048_eSMALL_MEM_CHAN_0_FIFO_2K     /* Chan 0 Fifo is 2k Bytes */
}ixf6048_UtopiaSmallMemCfg_e;
/* Configure whether impedance for unused UTOPIA signals
                  is held high, or not.; e.g. POS signals in ATM mode,
                  or Quad channel signals for Single Channel mode
                  - Reg R_UICNF bit 8 */
typedef enum   
{
   ixf6048_eUNUSED_UTOPIA_PINS_HIGH_IMP = 0,
   ixf6048_eUNUSED_UTOPIA_PINS_NOT_HIGH_IMP
} ixf6048_UnusedUtopiaPinsImp_e;

/* OrderWire Pulse byte configuration - OHPCNF bit 1 */
typedef enum
{
   ixf6048_eMSB_SAME_CLK_CYCLE_AS_PULSE = 0,
   ixf6048_eLSB_SAME_CLK_CYCLE_AS_PULSE
} ixf6048_OrderWirePulseByteLocn_e;

/* Overhead Port mode configuration - OHPCNF bit 0. 
   This option is only used in Quad Mode */
typedef enum
{
   ixf6048_eOH_PORT_LOGICAL_INTERFACE_NUM2 = 0,
   ixf6048_eOH_PORT_LOGICAL_INTERFACE_NUM3
} ixf6048_OverheadPortMode_e;


/* Input Clock Polarity Config - Set 1 - ICPCNF1 */
typedef ushort ixf6048_InClockPolarity1_e;   

#define	ixf6048_eTCI_T3_INVERTED   0x8000
#define ixf6048_eTCI_T2_INVERTED   0x4000
#define ixf6048_eTCI_T1_INVERTED   0x2000 
#define ixf6048_eTCI_T0_INVERTED   0x1000 

#define ixf6048_eRCI_T3_INVERTED   0x0800 
#define ixf6048_eRCI_T2_INVERTED   0x0400 
#define ixf6048_eRCI_T1_INVERTED   0x0200 
#define ixf6048_eRCI_T0_INVERTED   0x0100 

#define ixf6048_eTSCI_P3_INVERTED  0x0080 
#define ixf6048_eTSCI_P2_INVERTED  0x0040 
#define ixf6048_eTSCI_P1_INVERTED  0x0020 
#define ixf6048_eTSCI_P0_INVERTED  0x0010 

#define ixf6048_eRSCI_P3_INVERTED  0x0008 
#define ixf6048_eRSCI_P2_INVERTED  0x0004 
#define ixf6048_eRSCI_P1_INVERTED  0x0002 
#define ixf6048_eRSCI_P0_INVERTED  0x0001

/* Input Clock Polarity Config - Set 2 - ICPCNF2 */
typedef ushort ixf6048_InClockPolarity2_e;   
#define ixf6048_eTPCI_P_INVERTED 0x0002
#define ixf6048_eRPCI_P_INVERTED 0x0001

/* Output Clock Polarity Config - OCPCNF */
typedef ushort  ixf6048_OutClockPolarity_e;
#define ixf6048_eTCO_T3_INVERTED  0x8000 
#define ixf6048_eTCO_T2_INVERTED  0x4000 
#define ixf6048_eTCO_T1_INVERTED  0x2000 
#define ixf6048_eTCO_T0_INVERTED  0x1000 

#define ixf6048_eRCO_T3_INVERTED  0x0800 
#define ixf6048_eRCO_T2_INVERTED  0x0400 
#define ixf6048_eRCO_T1_INVERTED  0x0200 
#define ixf6048_eRCO_T0_INVERTED  0x0100 

#define ixf6048_eTSCO_P3_INVERTED 0x0080 
#define ixf6048_eTSCO_P2_INVERTED 0x0040 
#define ixf6048_eTSCO_P1_INVERTED 0x0020 
#define ixf6048_eTSCO_P0_INVERTED 0x0010 

#define ixf6048_eROWC_INVERTED	   0x0008 
#define ixf6048_eTOWC_INVERTED     0x0004 
/* ixf6048_eReserved               0x0002,   */
#define ixf6048_eTPCO_P_INVERTED   0x0001

/* Input Clock Monitoring Reg 1 - ICMR1 */
typedef ushort ixf6048_InClockMonitor1_e;   
#define ixf6048_eCHG_TCI_T3_INVERTED 0x8000 
#define ixf6048_eCHG_TCI_T2_INVERTED 0x4000 
#define ixf6048_eCHG_TCI_T1_INVERTED 0x2000 
#define ixf6048_eCHG_TCI_T0_INVERTED 0x1000 

#define ixf6048_eCHG_RCI_T3_INVERTED 0x0800 
#define ixf6048_eCHG_RCI_T2_INVERTED 0x0400 
#define ixf6048_eCHG_RCI_T1_INVERTED 0x0200 
#define ixf6048_eCHG_RCI_T0_INVERTED 0x0100 

#define ixf6048_eCHG_TSCI_P3_INVERTED 0x0080 
#define ixf6048_eCHG_TSCI_P2_INVERTED 0x0040 
#define ixf6048_eCHG_TSCI_P1_INVERTED 0x0020 
#define ixf6048_eCHG_TSCI_P0_INVERTED 0x0010 

#define ixf6048_eCHG_RSCI_P3_INVERTED 0x0008 
#define ixf6048_eCHG_RSCI_P2_INVERTED 0x0004 
#define ixf6048_eCHG_RSCI_P1_INVERTED 0x0002 
#define ixf6048_eCHG_RSCI_P0_INVERTED 0x0001

typedef ushort ixf6048_InClockMonitor2_e;   /* Input Clock Monitoring Reg 2 - ICMR2 */
#define ixf6048_eCHG_TXCLK_3_INVERTED 0x8000 
#define ixf6048_eCHG_TXCLK_2_INVERTED 0x4000 
#define ixf6048_eCHG_TXCLK_1_INVERTED 0x2000 
#define ixf6048_eCHG_TXCLK_0_INVERTED 0x1000 

#define ixf6048_eCHG_RXCLK_3_INVERTED 0x0800 
#define ixf6048_eCHG_RXCLK_2_INVERTED 0x0400 
#define ixf6048_eCHG_RXCLK_1_INVERTED 0x0200 
#define ixf6048_eCHG_RXCLK_0_INVERTED 0x0100 

#define ixf6048_eCHG_TPCI_P_INVERTED  0x0002 
#define ixf6048_eCHG_RPCI_P_INVERTED  0x0001

/*  ------- Non-Concatenation Mode Register Configuration --------- */
/* Configuration for the C0 byte generation from the SONET/SDH Mux
   See Reg NCMODECNF Bit 4 */
typedef enum
{
   ixf6048_eC0_BYTES_NOT_OVER_WRITTEN = 0,
   ixf6048_eC0_BYTES_OVER_WRITTEN
} ixf6048_J0MuxConfig_e;

/* Configuration for the way that the SONET/SDH Mux/Demux  
   interleaves/DeInterleaves the SONET/SDH Frames generated/received
   by each Tx Channel.
   See Reg NCMODECNF Bit 2, Bit 0 */
typedef enum
{
   ixf6048_eWORD_32_BIT_INTERLED = 0,
   ixf6048_eBYTE_INTERLEAVED
} ixf6048_MuxDemuxConfig_e;

/* Parity Mode Configuration 
      -- LPSCNF Bit 2 */
typedef enum
{