ixf6048b.h
来自「开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能」· C头文件 代码 · 共 1,460 行 · 第 1/5 页
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1,460 行
#define ixf6048_GET_B2_BIPCNT(BaseAddress,Chan) \
(READ_FROM_HW(BaseAddress + ixf6048_B2_BIPCNT_CHAN_LSB_OFFSET(Chan)) + \
((READ_FROM_HW(BaseAddress + ixf6048_B2_BIPCNT_CHAN_MSB_OFFSET(Chan))&0x3F) <<16 ))
/***********************************************************************
* Channel Counter Registers:MR_BLKCNT: MST REI Block Error Counter
* Page - (1cc)9A-99H
**********************************************************************/
#define ixf6048_MR_BLKCNT_CHAN_LSB_OFFSET(Chan) \
(((1<<10)+(0x99)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_MR_BLKCNT_CHAN_MSB_OFFSET(Chan) \
(((1<<10)+(0x9A)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_GET_MST_REI_BLKCNT(BaseAddress,Chan) \
(READ_FROM_HW(BaseAddress + ixf6048_MR_BLKCNT_CHAN_LSB_OFFSET(Chan)) + \
((READ_FROM_HW(BaseAddress + ixf6048_MR_BLKCNT_CHAN_MSB_OFFSET(Chan))&0x1) <<16 ))
/***********************************************************************
* Channel Counter Registers: MR_BIPCNT: MST REI BIP Error Counter
* Page - (1cc)9C-9BH
**********************************************************************/
#define ixf6048_MR_BIPCNT_CHAN_LSB_OFFSET(Chan) \
(((1<<10)+(0x9B)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_MR_BIPCNT_CHAN_MSB_OFFSET(Chan) \
(((1<<10)+(0x9C)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_MR_BIPCNT_MASK_M 0x001F
#define ixf6048_MR_BIPCNT_MASK_L 0xFFFF
#define ixf6048_GET_MST_REI_BIPCNT(BaseAddress,Chan) \
(READ_FROM_HW(BaseAddress + ixf6048_MR_BIPCNT_CHAN_LSB_OFFSET(Chan)) + \
((READ_FROM_HW(BaseAddress + ixf6048_MR_BIPCNT_CHAN_MSB_OFFSET(Chan))&0x1F) <<16 ))
/***********************************************************************
* Channel Registers: R_K2K1: Rx K1 & K2 Bytes
* Page - (1cc)9DH
**********************************************************************/
#define ixf6048_R_K2K1_CHAN_OFFSET(Chan) \
(((1<<10)+(0x9D)+(Chan<<8))<<REG_SHIFT)
/* To get K1 & K2, using ixf6048_RxMstBytes_t:
ushort Reg;
ixf6048_RxMstBytes_t RxMst;
Reg = ixf6048_GET_K1K2(BaseAddress,Chan);
RxMst.K1 = ixf6048_GET_K1(Reg);
RxMst.K2 = ixf6048_GET_K2(Reg);
*/
#define ixf6048_GET_K1K2(BaseAddress,Chan) \
(READ_FROM_HW(BaseAddress + ixf6048_R_K2K1_CHAN_OFFSET(Chan)))
#define ixf6048_GET_K1(K1K2) (K1K2&0x00FF)
#define ixf6048_MST_K1 0x00FF
#define ixf6048_MST_K1_SHIFT 0
#define ixf6048_GET_K2(K1K2) ((K1K2&0xFF00)>>8)
#define ixf6048_MST_K2 0xFF00
#define ixf6048_MST_K2_SHIFT 8
/***********************************************************************
* Channel Registers: R_S1: Rx S1 Byte
* Page - (1cc)9FH
**********************************************************************/
#define ixf6048_R_S1_CHAN_OFFSET(Chan) \
(((1<<10)+(0x9F)+(Chan<<8))<<REG_SHIFT)
/* To get S1, using ixf6048_RxMstBytes_t:
ixf6048_RxMstBytes_t RxMst;
RxMst.S1 = ixf6048_GET_S1(BaseAddress,Chan);
*/
#define ixf6048_GET_S1(BaseAddress,Chan) \
(READ_FROM_HW(BaseAddress + ixf6048_R_S1_CHAN_OFFSET(Chan))&0x00FF)
#define ixf6048_mRCV_S1 0x00FF
/***********************************************************************
* Channel Registers: WINSZ_SB2: Window Size for setting ExcB2ErrSt
* Page - (1cc)B0H
**********************************************************************/
#define ixf6048_WINSZ_SB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xB0)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_mEXC_B2_SET_WIN_SZ 0x07FF
#define ixf6048_SET_EXC_B2_WINDOW_SIZE(BaseAddress,Chan,WindowSize) \
(WRITE_TO_HW(BaseAddress + ixf6048_WINSZ_SB2_CHAN_OFFSET(Chan), \
(((WindowSize/8)-1) & ixf6048_mEXC_B2_SET_WIN_SZ)))
/***********************************************************************
* Channel Registers:
* CWIN_SB2: Consecutive Windows for setting ExcB2ErrSt
* Page - (1cc)B1H
* E_EXCWIN_SB2: Errs/Window for setting ExcB2ErrSt
* Page - (1cc)B2H
**********************************************************************/
#define ixf6048_CWIN_SB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xB1)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_EXCWIN_SB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xB2)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_mEXC_B2_SET_WIN_NUM 0x007F
#define ixf6048_mEXC_B2_MIN 0x0FFF
#define ixf6048_SET_EXC_B2_NUM_ERRS(BaseAddress,Chan,NumErrors) \
(WRITE_TO_HW(BaseAddress + ixf6048_CWIN_SB2_CHAN_OFFSET(Chan), \
(NumErrors & ixf6048_mEXC_B2_SET_WIN_NUM)))
#define ixf6048_SET_EXC_B2_NUM_WINDOWS(BaseAddress,Chan,NumWindows) \
(WRITE_TO_HW(BaseAddress + ixf6048_EXCWIN_SB2_CHAN_OFFSET(Chan), \
(NumWindows & ixf6048_mEXC_B2_MIN)))
/***********************************************************************
* Channel Registers: WINSZ_CB2: Window Size for clearing ExcB2ErrSt
* Page - (1cc)B3H
**********************************************************************/
#define ixf6048_WINSZ_CB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xB3)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_mEXC_B2_CLR_WIN_SZ 0x07FF
#define ixf6048_SET_CLR_EXC_B2_WINDOW_SIZE(BaseAddress,Chan,WindowSize) \
(WRITE_TO_HW(BaseAddress + ixf6048_WINSZ_CB2_CHAN_OFFSET(Chan), \
(((WindowSize/8)-1) & ixf6048_mEXC_B2_CLR_WIN_SZ)))
/***********************************************************************
* Channel Registers:
* CWIN_CB2: Consecutive Windows for clearing ExcB2ErrSt
* Page - (1cc)B4H
* E_NEXCWIN_CB2: Errs/Window for clearing ExcB2ErrSt
* Page - (1cc)B5H
**********************************************************************/
#define ixf6048_CWIN_CB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xB4)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_E_NEXCWIN_CB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xB5)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_mEXC_B2_CLR_WIN_NUM 0x007F
#define ixf6048_mEXC_B2_MAX 0x0FFF
#define ixf6048_SET_CLR_EXC_B2_NUM_ERRS(BaseAddress,Chan,NumErrors) \
(WRITE_TO_HW(BaseAddress + ixf6048_CWIN_CB2_CHAN_OFFSET(Chan), \
(NumErrors & ixf6048_mEXC_B2_CLR_WIN_NUM)))
#define ixf6048_SET_CLR_EXC_B2_NUM_WINDOWS(BaseAddress,Chan,NumWindows) \
(WRITE_TO_HW(BaseAddress + ixf6048_E_NEXCWIN_CB2_CHAN_OFFSET(Chan), \
(NumWindows & ixf6048_mEXC_B2_MAX)))
/***********************************************************************
* Channel Registers: WINSZ_SDEGB2: Window Size for setting DegB2ErrSt
* Page - (1cc)B7-B6H
**********************************************************************/
#define ixf6048_WINSZ_SDEGB2_CHAN_LSB_OFFSET(Chan) \
(((1<<10)+(0xB6)+(Chan<<8))<<REG_SHIFT) /* Offset of LSB */
#define ixf6048_WINSZ_SDEGB2_CHAN_MSB_OFFSET(Chan) \
(((1<<10)+(0xB7)+(Chan<<8))<<REG_SHIFT) /* Offset of MSB */
#define ixf6048_DEG_B2_SET_WINSZ_MASK_M 0x007F
#define ixf6048_DEG_B2_SET_WINSZ_MASK_L 0xFFFF
/* Note: Window Size Must be a 32 Bit Value */
#define ixf6048_SET_LSB_SDEGB2_WINDOW_SIZE(BaseAddress,Chan,WindowSize) \
(WRITE_TO_HW(BaseAddress + ixf6048_WINSZ_SDEGB2_CHAN_LSB_OFFSET(Chan), \
(ushort) (((WindowSize/8)-1)&0x0000FFFF)))
#define ixf6048_SET_MSB_SDEGB2_WINDOW_SIZE(BaseAddress,Chan,WindowSize) \
(WRITE_TO_HW(BaseAddress + ixf6048_WINSZ_SDEGB2_CHAN_MSB_OFFSET(Chan), \
(ushort) ((((WindowSize/8)-1)&0x00FF0000)>>16)))
/***********************************************************************
* Channel Registers:
* WINSZ_SDEGB2: Consecutive Windows for setting DegB2ErrSt
* Page - (1cc)B8H
* E_DEGWIN_SB2: Errs/Window for setting DegB2ErrSt
* Page - (1cc)B9H
**********************************************************************/
#define ixf6048_CWIN_SDEGB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xB8)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_E_DEGWIN_SB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xB9)+(Chan<<8)) <<REG_SHIFT)
#define ixf6048_CWIN_SDEGB2_MASK 0x007F
#define ixf6048_E_DEGWIN_SB2_MASK 0x0FFF
#define ixf6048_SET_DEG_B2_ERRORS(BaseAddress,Chan,NumErrors) \
(WRITE_TO_HW(BaseAddress + ixf6048_CWIN_SDEGB2_CHAN_OFFSET(Chan), \
(NumErrors & ixf6048_CWIN_SDEGB2_MASK)))
#define ixf6048_SET_DEG_B2_WINDOWS(BaseAddress,Chan,NumWindows) \
(WRITE_TO_HW(BaseAddress + ixf6048_E_DEGWIN_SB2_CHAN_OFFSET(Chan), \
(NumWindows & ixf6048_E_DEGWIN_SB2_MASK)))
/***********************************************************************
* Channel Registers: WINSZ_CDEGB2: Window Size for clearing DegB2ErrSt
* Page - (1cc)BB-BAH
**********************************************************************/
#define ixf6048_WINSZ_CDEGB2_CHAN_LSB_OFFSET(Chan) \
(((1<<10)+(0xBA)+(Chan<<8))<<REG_SHIFT) /* Offset of LSB */
#define ixf6048_WINSZ_CDEGB2_CHAN_MSB_OFFSET(Chan) \
(((1<<10)+(0xBB)+(Chan<<8))<<REG_SHIFT) /* Offset of MSB */
/* Note: Window Size MUST be a 32 Bit Value */
#define ixf6048_SET_CLR_LSB_DEGB2_WINDOW_SIZE(BaseAddress,Chan,WindowSize) \
(WRITE_TO_HW(BaseAddress + ixf6048_WINSZ_CDEGB2_CHAN_LSB_OFFSET(Chan), \
(ushort) (((WindowSize/8)-1)&0x0000FFFF)))
#define ixf6048_SET_CLR_MSB_DEGB2_WINDOW_SIZE(BaseAddress,Chan,WindowSize) \
(WRITE_TO_HW(BaseAddress + ixf6048_WINSZ_CDEGB2_CHAN_MSB_OFFSET(Chan), \
(ushort) ((((WindowSize/8)-1)&0x00FF0000)>>16)))
/***********************************************************************
* Channel Registers:
* CWIN_CDEGB2: Consecutive Windows for clearing DegB2ErrSt
* Page - (1cc)BCH
* E_NDEGWIN_CB2: Errs/Window for clearing DegB2ErrSt
* Page - (1cc)BDH
**********************************************************************/
#define ixf6048_CWIN_CDEGB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xBC)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_E_NDEGWIN_CB2_CHAN_OFFSET(Chan) \
(((1<<10)+(0xBD)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_CWIN_CDEGB2_MASK 0x007F
#define ixf6048_E_NDEGWIN_CB2_MASK 0x0FFF
#define ixf6048_SET_CLEAR_DEG_B2_ERRORS(BaseAddress,Chan,NumErrors) \
(WRITE_TO_HW(BaseAddress + ixf6048_CWIN_CDEGB2_CHAN_OFFSET(Chan), \
(NumErrors & ixf6048_CWIN_CDEGB2_MASK)))
#define ixf6048_SET_CLEAR_DEG_B2_WINDOWS(BaseAddress,Chan,NumWindows) \
(WRITE_TO_HW(BaseAddress + ixf6048_E_NDEGWIN_CB2_CHAN_OFFSET(Chan), \
(NumWindows & ixf6048_E_NDEGWIN_CB2_MASK)))
/***********************************************************************
* Channel Registers:
* IS_MUX: Rx MST Interrupt Source
* Page - (1cc)D1H
* IE_MUX: Rx MST Interrupt Enable
* Page - (1cc)D5H
* S_MUX: Rx MST Status
* Page - (1cc)D9H
**********************************************************************/
#define ixf6048_IS_MUX_CHAN_OFFSET(Chan) \
(((1<<10)+(0xD1)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_IE_MUX_CHAN_OFFSET(Chan) \
(((1<<10)+(0xD5)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_S_MUX_CHAN_OFFSET(Chan) \
(((1<<10)+(0xD9)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_mIS_MUX 0x7FFF
#define ixf6048_mIE_MUX 0x7FFF
#define ixf6048_mS_MUX 0x00FF
#define ixf6048_eRX_MST_S1_ALM 0x4000 /* Change in Rx S1 byte */
#define ixf6048_eRX_MST_K1_ALM 0x2000 /* Change in Rx K1 */
#define ixf6048_eRX_MST_K2_ALM 0x1000 /* Change in Rx K2 */
#define ixf6048_eRX_MST_B2_BIT_OVFL_ALM 0x0800 /* B2 Bit err cntr overflowed */
#define ixf6048_eRX_MST_B2_BLK_OVFL_ALM 0x0400 /* B2 Block err cntr overflowed */
#define ixf6048_eRX_MST_REI_BIT_OVFL_ALM 0x0200 /* REI Bit err cntr overflowed */
#define ixf6048_eRX_MST_REI_BLK_OVFL_ALM 0x0100 /* REI Block err cntr overflowed */
#define ixf6048_eRX_MST_S8_UNSTABLE_ALM 0x0080 /* Change in Rx S1 byte unstable */
#define ixf6048_eRX_MST_K9_UNSTABLE_ALM 0x0040 /* Change in Rx K1 byte unstable */
#define ixf6048_eRX_MST_K2_UNSTABLE_ALM 0x0020 /* Change in Rx K2 byte unstable */
#define ixf6048_eRX_MST_DEG_B2_ERR_ALM 0x0010 /* Change in Degraded B2 err stat */
#define ixf6048_eRX_MST_SF_ALM 0x0008 /* Change in MST SF status */
#define ixf6048_eRX_MS⌨️ 快捷键说明
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