📄 ixf6048b.h
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#define ixf6048_bRST_AIS_LOCKN 0x0020
#define ixf6048_bRST_AIS_TIMN 0x0008
#define ixf6048_mRCV_LOS_CNFG 0x0600
#define ixf6048_RCV_LOS_CNFG_ON_25US_LOS_EN 0x0600
#define ixf6048_RCV_LOS_CNFG_ON_25US_ZEROS_EN 0x0400
#define ixf6048_RCV_LOS_CNFG_ON_20US_LOS_EN 0x0200
#define ixf6048_RCV_LOS_CNFG_ON_20US_ZEROS_EN 0x0000
#define ixf6048_SET_RST_RCV_LOS_CNFG(Reg, LosVal) \
(Reg |= (LosVal<<9) & ixf6048_mRCV_LOS_CNFG)
#define ixf6048_bRST_CLK_LOCK_EN 0x0100 /* 1 = Auto Clk Switch because of LOCK or LOS */
#define ixf6048_bRST_AIS_LOF_EN 0x0080 /*1 -> AIS Generation during LOF */
#define ixf6048_bRST_AIS_LOS_EN 0x0040 /*1 -> AIS Generation during LOS */
#define ixf6048_bRST_AIS_LOCK_EN 0x0020 /*1 -> AIS Generation during LOCK */
#define ixf6048_bRST_AIS_FRC 0x0010 /*1 -> Force AIS gen from the RST
section to the MST section via software*/
#define ixf6048_bRST_AIS_TIM_EN 0x0008 /*1 -> Enable AIS during active j0MsMtchSt */
#define ixf6048_mLOCK_ITG 0x0006 /* Configure LOCK alarm Filtering Mask */
#define ixf6048_NO_LOCK_FILTERING_EN 0x0000 /* Bit 2 = 0 For No Filtering */
#define ixf6048_WEAK_LOC_FILTERING_EN 0x0004 /* Weak LOCK filtering */
#define ixf6048_STRONG_LOC_FILTERING_EN 0x0006 /* Strong LOCK Filtering */
#define ixf6048_SET_LOCK_ITG(Reg, FilterVal) \
(Reg |= (FilterVal<<1) & ixf6048_mLOCK_ITG)
#define ixf6048_bCNFG_FRM_ACQ 0x0001 /*1 -> Robust Acquisition */
/***********************************************************************
* Channel Registers: LOF_LMN: Loss of Frame L, M, & N Configuration
* Page - (1cc)81H
*
* To Set L,M,N:
* ushort Reg;
* ushort* BaseAddress;
*
* Reg = 0;
* ixf6048_STORE_L (L, Reg);
* ixf6048_STORE_M (M, Reg);
* ixf6048_STORE_N (N, Reg);
* *(BaseAddress + ixf6048_LOF_LMN_CHAN_OFFSET(Chan)) |= Reg;
**********************************************************************/
#define ixf6048_LOF_LMN_CHAN_OFFSET(Chan) \
(((1<<10)+(0x81)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_bRCV_OOF_CNFG 0x8000 /* Out of Frame Config Bit */
#define ixf6048_bL_LOF_LMN 0x7C00 //L
#define ixf6048_bM_LOF_LMN 0x03E0 //M
#define ixf6048_bN_LOF_LMN 0x001F //N
#define ixf6048_STORE_L(LMN, L) \
LMN |= (((L-1)&0x1F)<<10)
#define ixf6048_STORE_M(LMN, M) \
LMN |= (((M-1)&0x1F)<<5)
#define ixf6048_STORE_N(LMN, N) \
LMN |= ((N-1)&0x1F)
/***********************************************************************
* Channel Counter Registers: OOF_ECNT: Out of Frame Event Counter
* Page - (1cc)82H
**********************************************************************/
#define ixf6048_OOF_ECNT_CHAN_OFFSET(Chan) \
(((1<<10)+(0x82)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_OOF_ECNT 0x1FFF
#define ixf6048_GET_OOF_CNT(BaseAddress,Chan) \
(READ_FROM_HW(BaseAddress + ixf6048_OOF_ECNT_CHAN_OFFSET(Chan)) & 0x1FFF)
/***********************************************************************
* Channel Counter Registers: B1_ERRCNT: B1 Error Counter
* Page - (1cc)83H
**********************************************************************/
#define ixf6048_B1_ERRCNT_CHAN_OFFSET(Chan) \
(((1<<10)+(0x83)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_B1_ERRCNT 0xFFFF
#define ixf6048_GET_B1_ERRCNT(BaseAddress,Chan) \
(READ_FROM_HW(BaseAddress + ixf6048_B1_ERRCNT_CHAN_OFFSET(Chan)))
/***********************************************************************
* Channel Registers:
* R_J0_ESTRA: J0 Rx Expected String Data Access
* Page - (1cc)85H
* R_J0_ASTRA: J0 Rx Accepted String Data Access
* Page - (1cc)86H
*
* R_J1_ESTRA: J1 Rx Expected String Data Access
* Page - (1cc)ADH
* T_J1_TSTRA: J1 Tx String Data Access
* Page - (1cc)AFH
*
* T_J0_TSTRA: J0 Tx String Data Access
* Page - (1cc)E4H
* R_J1_ASTRA: J1 Rx Accepted String Data Access
* Page - (1cc)EEH
*
* Trace = EXPECTED/RX/TX_J0/J1, e.g. EXPECTED_J0
*
* To Write Trace Byte:
* while(! ixf6048_CAN_WRITE_TRACE(TX_J0, 0x1200, 0))
* ; [wait until can write new trace byte]
* ixf6048_WRITE_TRACE(TX_J0, 0x1200, 0, ByteIdx,TraceByte);
*
* To Read Trace Byte:
* Set the Trace Read Bit
* ixf6048_READ_TRACE(pReg, iByteIndex, pWorkString++);
* Wait for the Read Access
* while(!(ixf6048_READ_TRACE_DONE(*pReg)));
* Mask out the Byte
* CharByte = ixf6048_GET_TRACE_BYTE(*pReg);
*
**********************************************************************/
#define ixf6048_EXPECTED_J0_CHAN_OFFSET(Chan) \
(((1<<10)+(0x85)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_RX_J0_CHAN_OFFSET(Chan) \
(((1<<10)+(0x86)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_RX_J1_CHAN_OFFSET(Chan) \
(((1<<10)+(0xAD)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_EXPECTED_J1_CHAN_OFFSET(Chan) \
(((1<<10)+(0xAF)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_TX_J0_CHAN_OFFSET(Chan) \
(((1<<10)+(0xE4)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_TX_J1_CHAN_OFFSET(Chan) \
(((1<<10)+(0xEE)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_CAN_WRITE_TRACE(pReg) ((READ_FROM_HW(pReg) & 0x8000) == 0)
#define ixf6048_WRITE_TRACE(pReg, ByteIdx, TraceByte) \
WRITE_TO_HW(pReg, (0x8000 + (ByteIdx<<8) + (*TraceByte)))
#define ixf6048_READ_TRACE(pReg, ByteIdx) \
(WRITE_TO_HW(pReg, (0x4000 + (ByteIdx<<8))))
#define ixf6048_READ_TRACE_DONE(TraceReg) \
((TraceReg & 0x4000) == 0)
#define ixf6048_GET_TRACE_BYTE(TraceReg) \
(TraceReg & 0x00FF)
#define ixf6048_mEXP_J0_STRG_ADDR 0x3F00 /* Bits [13:8] represents the string pointer value (RAM address). Whenever Microprocessor access this register to read, this address will be automatically increased to next address. */
#define ixf6048_mEXP_J0_STRG_DATA 0x00FF /* Bits [7:0] represents the data value. */
#define ixf6048_mEXP_J0_STRG_ADDR_SHFT 8 /* Shift Value for Slot Index */
/***********************************************************************
* Channel Registers: J0_RSTC: J0 Received Trace Configuration
* Page - (1cc)87H
**********************************************************************/
#define ixf6048_J0_RSTC_CHAN_OFFSET(Chan) \
(((1<<10)+(0x87)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_bRS_TIM_ON_CRC7_ERR_DSB 0x0020 /* Config setting of RS-Tim Alm*/
/* When CRC-7 is wrong */
#define ixf6048_bRS_TIM_ON_UNSTABLE_EN 0x0010 /* Config setting of RS-Tim Alm*/
/* When Trace is unstable */
#define ixf6048_bRCV_J0_STABLE_CNFG 0x0008 /* 1- 5 Consectutive identical Messages*/
#define ixf6048_mRCV_J0_CNF 0x0007 /* Mask for Configure J0 Rx Trace Id Format */
#define ixf6048_RX_JN_64_WITH_LF_CR_EN 0x0007
#define ixf6048_RX_JN_64_FREE_FORM_EN 0x0006
#define ixf6048_RX_JN_16_WITH_CRC7_EN 0x0004
#define ixf6048_IGNORE_RX_JN_EN 0x0002
#define ixf6048_RX_JN_1_BYTE_EN 0x0000
#define ixf6048_GET_RCV_J0_CNF_FORMAT(Reg) (Reg & ixf6048_mRCV_J0_CNF)
#define ixf6048_SET_RCV_J0_CNF_FORMAT(Reg, NewFormat) \
(Reg = ((Reg & ~ixf6048_mRCV_J0_CNF) | NewFormat) )
/***********************************************************************
* Channel Registers:
* IS_RG: Rx RST Interrupt Source
* Page - (1cc)D0H (COR)
* IE_RG: Rx RST Interrupt Enable
* Page - (1cc)D4H
* S_RG: Rx RST Status
* Page - (1cc)D8H
**********************************************************************/
#define ixf6048_IS_RG_CHAN_OFFSET(Chan) \
(((1<<10)+(0xD0)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_RX_RST_OOF_OVFL_ALM 0x0200
#define ixf6048_RX_RST_B1_OVFL_ALM 0x0100
#define ixf6048_RX_RST_J0_UNSTABLE_ALM 0x0040
#define ixf6048_RX_RST_J0_MISMATCH_ALM 0x0020
#define ixf6048_RX_RST_J0_CRC7_ALM 0x0010
#define ixf6048_RX_RST_LOS_ALM 0x0008
#define ixf6048_RX_RST_LO_CLK_ALM 0x0004
#define ixf6048_RX_RST_LOF_ALM 0x0002
#define ixf6048_RX_RST_OOF_ALM 0x0001
#define ixf6048_IE_RG_CHAN_OFFSET(Chan) \
(((1<<10)+(0xD4)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_S_RG_CHAN_OFFSET(Chan) \
(((1<<10)+(0xD8)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_mIS_RG 0x037F /* Interupt Reg Mask */
#define ixf6048_mIE_RG 0x037F /* Interupt Enable Reg Mask */
#define ixf6048_mS_RG 0x007F /* Interupt Status Reg Mask */
/* See ixf6048_RxRstAlarms_e */
/***********************************************************************
* Channel Registers: R_MST_C: Rx MST Configuration
* Page - (1cc)90H
**********************************************************************/
#define ixf6048_R_MST_C_CHAN_OFFSET(Chan) \
(((1<<10)+(0x90)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_mR_MST_C 0x27FF
/* See ixf6048_RxMstCfg_t for Settings
-- see also IS_MUX (1cc)D1H */
#define ixf6048_bMST_APS_FILT_CNFG 0x2000
#define ixf6048_bMST_AIS_DET_CNT 0x0400
#define ixf6048_mMST_RDI_DET_CNT 0x0300
#define ixf6048_K2_RDI_DETECT_IN_3_FRAMES_EN 0x0000
#define ixf6048_K2_RDI_DETECT_IN_5_FRAMES_EN 0x0100
#define ixf6048_K2_RDI_DETECT_IN_10_FRAMES_EN 0x0200
#define ixf6048_K2_RDI_DETECT_IN_16_FRAMES_EN 0x0300
/* Set from ixf6048_K2RdiDetect_e Value */
#define ixf6048_SET_K2_RDI_DETECT(Reg, DetRdiVal) \
(Reg = (Reg | ((DetRdiVal << 8) & ixf6048_mMST_RDI_DET_CNT)))
#define ixf6048_bAIS_ON_EXC_B2_EN 0x0080
#define ixf6048_MST_AIS_FRC 0x0040 /* Force Tx AIS -- used for Testing */
#define ixf6048_MST_AIS_EN 0x0020
#define ixf6048_MST_GEN_REI_CNF 0x0010
#define ixf6048_MST_RCV_REI_CNF 0x0008
#define ixf6048_MST_RDI_ON_EXC_B2_EN 0x0004
#define ixf6048_MST_RDI_FRC 0x0002 /* Force Tx RDI -- used for Testing */
#define ixf6048_MST_BLK_ERR_CNFG 0x0001 /* 1 -> Multiple Blocks Per Frame */
/***********************************************************************
* Channel Counter Registers: B2_BLKCNT: B2 Block Error Counter
* Page - (1cc)96-95H
**********************************************************************/
#define ixf6048_B2_BLKCNT_CHAN_LSB_OFFSET(Chan) \
(((1<<10)+(0x95)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_B2_BLKCNT_CHAN_MSB_OFFSET(Chan) \
(((1<<10)+(0x96)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_B2_BLK_CNT_MASK_M 0x0001
#define ixf6048_B2_BLK_CNT_MASK_L 0xFFFF
#define ixf6048_GET_B2_BLKCNT(BaseAddress,Chan) \
(READ_FROM_HW(BaseAddress + ixf6048_B2_BLKCNT_CHAN_LSB_OFFSET(Chan)) + \
((READ_FROM_HW(BaseAddress + ixf6048_B2_BLKCNT_CHAN_MSB_OFFSET(Chan))&0x1) <<16 ))
/***********************************************************************
* Channel Counter Registers: B2_BIPCNT: B2 BIP Error Counter
* Page - (1cc)98-97H
**********************************************************************/
#define ixf6048_B2_BIPCNT_CHAN_LSB_OFFSET(Chan) \
(((1<<10)+(0x97)+(Chan<<8))<<REG_SHIFT)/* Offset of LSB */
#define ixf6048_B2_BIPCNT_CHAN_MSB_OFFSET(Chan) \
(((1<<10)+(0x98)+(Chan<<8))<<REG_SHIFT) /* Offset of MSB */
#define ixf6048_B2_CNT_MASK_M 0x003F
#define ixf6048_B2_BIP_CNT_MASK_L 0xFFFF
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