📄 ixf6048b.h
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* Global Registers: LSPCNF: Line Side Parity Configuration register
* Page - (000)H
**********************************************************************/
#define ixf6048_LSPCNF_OFFSET (0x1E << REG_SHIFT)
#define ixf6048_bPRTY_MODE_CNF 0x0004 /* Protect parallel data bus plus Frame Pulse */
#define ixf6048_bRCV_PRTY_CNF 0x0002 /* 1 - Serves as even parity */
#define ixf6048_bXMT_PRTY_CNF 0x0001 /* 1 serves as even parity */
/***********************************************************************
* Global Registers: LSPINT: Line Side Parity Interupt register
* Page - (000)H
**********************************************************************/
#define ixf6048_LSPINT_OFFSET (0x1F << REG_SHIFT)
#define ixf6048_mLSP_INT 0x0001 /* LSP Interupt mask */
/***********************************************************************
* Global Registers: LSPINTEN: Line Side Parity Interupt Enable register
* Page - (000)H
**********************************************************************/
#define ixf6048_LSPINTEN_OFFSET (0x20 << REG_SHIFT)
/***********************************************************************
* Global Registers: MISC_GIS: Miscelaneous Global Interupt Source register
* Page - (000)H
**********************************************************************/
#define ixf6048_MISC_GIS_OFFSET (0x21 << REG_SHIFT)
#define ixf6048_mMISC_GIS_INT 0x001F /* MISC GIS Interupt Mask */
#define ixf6048_MISC_PRBS_INT 0x0010
#define ixf6048_MISC_TALB_INT 0x0008
#define ixf6048_MISC_LSP_INT 0x0004
#define ixf6048_MISC_XMTUTOP_INT 0x0002
#define ixf6048_MISC_RCVUTOP_INT 0x0001
/***********************************************************************
* UTOPIA INTERFACE REGISTERS
*
**********************************************************************/
/***********************************************************************
* Global Register: R_UICNF: Rx UTOPIA i/f Configuration
* Page - (000)70H
**********************************************************************/
#define ixf6048_R_UICNF_OFFSET (0x70 << REG_SHIFT)
#define ixf6048_mR_UICNF 0x07FF /* Register Mask Read/Write*/
/* PSN_ADDED Added for B1 Release */
#define ixf6048_bRCV_VAL2_CNF 0x0800 /* reading blocked after EOF */
/* PSN_END B1 RElease Changes */
#define ixf6048_bRCV_ATM_HEC 0x0400 /* 1 - 2 status bits are passed */
#define ixf6048_bRCV_SMALL_MEM 0x0200 /* 1 = 2K FIFO; 0 = 16K FIFO */
#define ixf6048_bRCV_TEST_O_EN 0x0100 /* Unused signals not high imp */
/* Note: This is always = 0 */
#define ixf6048_bRCV_VAL_CNF 0x0080 /* RXVal deassert on End of Pkt */
#define ixf6048_bRCV_FIF_EMPT_EOF 0x0040 /* RXFA_i deassert, even if EOF */
/* The Remainder of bits common to Rx/Tx i/f -- See Register (000)50H - T_UICNF*/
#define ixf6048_bRX_TX_DIR_STAT_CNF 0x0020 /* Rx/TxFA: Multiplexed status */
#define ixf6048_bRX_TX_M_PHY_DEV_CNF 0x0010 /* Config Receive Interface -- See Spec */
#define ixf6048_bRX_TX_U_QUAD 0x0008 /* UTOPIA Multi-PHY Single/Quad */
#define ixf6048_mRX_TX_U_WIDTH 0x0006 /* Mask for following Bits */
#define ixf6048_U_WIDTH_QUAD_SINGLE_8BIT 0x0000 /* Single/Quad Chan,8-bit UTOPIA i/f */
#define ixf6048_U_WIDTH_QUAD_SINGLE_16BIT 0x0002 /* Single/Wuad Chan,16-bit UTOPIA i/f. Bit 3 MUST be 0*/
#define ixf6048_U_WIDTH_SINGLE_32BIT 0x0004 /* Single Chan, 32-bit UTOPIA i/f. Bit 3 MUST be 0*/
#define ixf6048_U_WIDTH_SINGLE_64BIT 0x0006 /* Single Chan, 64-bit UTOPIA i/f. Bit 3 MUST be 0*/
#define ixf6048_SET_U_WIDTH(Reg, Width) \
(Reg = (Reg & ~ixf6048_mRX_TX_U_WIDTH) | (Width & ixf6048_mRX_TX_U_WIDTH))
#define ixf6048_bRCV_XMT_SEL_MODE 0x0001 /* POS UTOPIA interface is mem mapped */
/* PSN_TODO -- Where does this Fit? */
#define ixf6048_FIFO_RESTART_LEVEL(NumBytes) \
((((NumBytes-1)/64)<<1)&0x7E) /* Rx/Tx FIFO Restart Level */
/***********************************************************************
* Global Register: R_UIIML: Rx UTOPIA Interface Initiation
* Minimum Level
* Page - (000)71H
**********************************************************************/
#define ixf6048_R_UIIML_OFFSET (0x71 << REG_SHIFT)
#define ixf6048_mR_UIIML 0x00FF /* Mask for Rx UTOPIA IIML */
/***********************************************************************
* Channel Registers: R_UICHCNF: Rx UTOPIA i/f Channel Configuration
* Page - (0cc)60H
**********************************************************************/
#define ixf6048_R_UICHCNF_CHAN_OFFSET(Chan) \
(((0x60)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_R_UICHCNF_CHAN_MASK 0x0FFF /* Register Access Mask */
/* All bits common to Rx/Tx i/f for channel */
#define ixf6048_bBURST_CNF 0x0800 /* Rx/TxFA Active low */
#define ixf6048_bF_A_CNF 0x0400 /* Rx/TxFA Active low */
#define ixf6048_bPRTY_CNF 0x0200 /* 1 = Even Parity */
#define ixf6048_bD_R_CNF 0x0100 /* 1 - 2 Clk Delay in Utopia Interface */
/* Device Rx from SONET/SDH */
/* Device Tx to SONET/SDH */
#define ixf6048_bFIFO_RST 0x0080 /* Set, to Halt Chan Rx/Tx (FIFO_Rst) */
/* Clr, to Restart Chan Rx/Tx */
#define ixf6048_bCELL_STRUCT 0x0040 /* Pass NULL HEC Word */
#define ixf6048_mC_A_DEASSERT 0x3F /* For Rx/Tx */
#define ixf6048_SET_C_A_DEASSERT(Reg, CadVal) \
(Reg = (Reg & ~ixf6048_mC_A_DEASSERT) | (CadVal & ixf6048_mC_A_DEASSERT) )
/***********************************************************************
* Channel Registers: R_PWM: Rx Programmable Watermark
* Page - (0cc)61H
* **********************************************************************/
#define ixf6048_R_PWM_CHAN_OFFSET(Chan) \
(((0x61)+(Chan<<8))<<REG_SHIFT)
/* Note: See Reg T_NFPWM (Below) for definition of
ixf6048_SET_WATERMARK and Mask Definitions */
/***********************************************************************
* Global Register: T_UICNF: Tx UTOPIA i/f Configuration
* Page - (000)50H
**********************************************************************/
#define ixf6048_T_UICNF_OFFSET (0x50<<REG_SHIFT)
#define ixf6048_mT_UICNF 0x00FF /* Register Mask Read/Write*/
#define ixf6048_bXMT_SMALL_MEM 0x0080 /* 1 = 2K FIFO; 0 = 16K FIFO */
/* Note: This is always = 0 */
#define ixf6048_XMT_FIF_EMPT_EOF 0x0040 /* RXFA_i deassert, even if EOF */
/* Note: The Remaining Bits are common to Register R_UICNF and have
been Defined There */
/***********************************************************************
* Global Register: T_UIIML: Tx UTOPIA Interface Initiation
* Minimum Level
* Page - (000)51H
**********************************************************************/
#define ixf6048_T_UIIML_OFFSET (0x51<<REG_SHIFT)
#define ixf6048_mT_UIIML 0x00FF /* Mask for Tx UTOPIA IIML */
/***********************************************************************
* Channel Registers: T_UICHCNF: Tx UTOPIA i/f Channel Configuration
* Page - (0cc)40H
**********************************************************************/
#define ixf6048_T_UICHCNF_CHAN_OFFSET(Chan) \
(((0x40)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_mT_UICHCNF_CHAN 0x07FF /* Register Access Mask */
/* Note: All bit Masks for this register are common to
register (0cc)60H and have been defined there. */
/***********************************************************************
* Channel Registers: T_UIFDP: UTOPIA Interface FIFO depth
* Page - (0cc)41H
**********************************************************************/
#define ixf6048_T_UIFDP_CHAN_OFFSET(Chan) \
(((0x41)+(Chan<<8))<<REG_SHIFT)
/* Fifo Depth Mask */
#define ixf6048_mXMT_F_D_CNF_CHAN_0 0xFF /* ChanMask for Chan 0 */
#define ixf6048_mXMT_F_D_CNF_CHANS_1_3 0x1F /* ChanMask for Channels 1-3 */
#define ixf6048_SET_XMT_F_D_CNF(Reg, FifoDepth, ChanMask) \
(Reg = (FifoDepth & ChanMask) )
/***********************************************************************
* Channel Registers:
* T_NFPWM: Tx Near Full Programmable Watermark
* Page - (0cc)42H
* T_NEPWM: Tx Near Empty Programmable Watermark
* Page - (0cc)43H
**********************************************************************/
#define ixf6048_T_NFPWM_CHAN_OFFSET(Chan) \
(((0x42)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_T_NEPWM_CHAN_OFFSET(Chan) \
(((0x43)+(Chan<<8))<<REG_SHIFT)
/* [11:0] Bits are available for Chan 0,
[8:0] Bits are available for Chan 1-3 */
#define ixf6048_mWATERMARK_CHAN_0 0x0FFF
#define ixf6048_mWATERMARK_CHAN_1_3 0x01FF
#define ixf6048_SET_WATERMARK(Reg, NumBytes, WatermarkMask) \
(Reg = NumBytes & WatermarkMask)
/* Note: ixf6048_WATERMARK is used also for R_PWM register */
/***********************************************************************
* Global Registers:
* R_UTOINT: Rx UTOPIA Interrupt
* Page - (000)72H (COR)
* T_UTOINT: Tx UTOPIA Interrupt
* Page - (000)52H (COR)
* These alarms put together to form: ixf6048_UtopiaAlarms_t
**********************************************************************/
#define ixf6048_R_UTOINT_OFFSET (0x72<<REG_SHIFT)
#define ixf6048_T_UTOINT_OFFSET (0x52<<REG_SHIFT)
#define ixf6048_mR_UTOINT 0x000F /* MASK RX FIFO UFI interupts */
#define ixf6048_mT_UTOINT 0x0FFF /* Mask ALL TX UTOPIA Interupts */
#define ixf6048_mRCV_FIFO_OF_INT 0x00F0 /* Rx FIFO Overflow Interupt */
#define ixf6048_SHIFT_RCV_FIFO_OF_INT(Chan) ( 0x0010 << Chan )
#define ixf6048_mRCV_FIFO_UF_INT 0x000F /* Rx FIFO Underflow Interupt */
#define ixf6048_SHIFT_RCV_FIFO_UF_INT(Chan) ( 0x0001 << Chan )
#define ixf6048_mTX_FIFO_UF_INT 0xF000 /* Tx FIFO Underflow Interupt*/
#define ixf6048_SHIFT_TX_FIFO_UF_INT(Chan) ( 0x1000 << Chan )
#define ixf6048_mXMT_SOC_INT 0x0F00 /* Start Of Cell Interupt */
#define ixf6048_SHIFT_XMT_SOC_INT(Chan) ( 0x0100 << Chan )
#define ixf6048_mTX_PRTY_ERR_INT 0x00F0 /* Parity Error Interupt */
#define ixf6048_SHIFT_TX_PRTY_ERR_INT(Chan) ( 0x0010 << Chan )
#define ixf6048_mTX_FIFO_OF_INT 0x000F /* Tx FIFO Overflow Interupt*/
#define ixf6048_SHIFT_TX_FIFO_OF_INT(Chan) ( 0x0001 << Chan )
#define ixf6048_GET_R_UTOPIA_INT_CHAN_MASK(Chan) (ixf6048_mR_UTOINT & (0x1111 << Chan))
#define ixf6048_GET_T_UTOPIA_INT_CHAN_MASK(Chan) (ixf6048_mT_UTOINT & (0x1111 << Chan))
/***********************************************************************
* Global Registers:
* R_UTOINT: Rx UTOPIA Interrupt Enable
* Page - (000)73H
* T_UTOINT: Tx UTOPIA Interrupt Enable
* Page - (000)53H
* These alarms put together to form: ixf6048_UtopiaAlarms_t
**********************************************************************/
#define ixf6048_R_UTOINTEN_OFFSET (0x73<<REG_SHIFT)
#define ixf6048_T_UTOINTEN_OFFSET (0x53<<REG_SHIFT)
#define ixf6048_mRX_FIFO_UF_INT_EN 0x000F /* Tx/Rx FIFO Underflow Interupts EN*/
/* Note: See Interupt Register for Masks */
/*#define ixf6048_mTX_SOC_INT_EN 0x0F00 *//* Start Of Cell Interupts EN */
/*#define ixf6048_mTX_PRTY_ERR_INT_EN 0x00F0 *//* Parity Error Interupts EN */
/*#define ixf6048_mTX_FIFO_OF_INT_EN 0x000F *//* Tx/Rx FIFO Underflow Interupts EN*/
#define ixf6048_SHIFT_RX_FIFO_OF_INT_EN(Chan) (0x0010 << Chan)
#define ixf6048_SHIFT_RX_FIFO_UF_INT_EN(Chan) (0x0001 << Chan)
#define ixf6048_SHIFT_TX_FIFO_UF_INT_EN(Chan) (0x1000 << Chan)
#define ixf6048_SHIFT_TX_SOC_INT_EN(Chan) (0x0100 << Chan)
#define ixf6048_SHIFT_TXPRTY_ERR_INT_EN(Chan) (0x0010 << Chan)
#define ixf6048_SHIFT_TX_FIFO_OF_INT_EN(Chan) (0x0001 << Chan)
/***********************************************************************
* Channel Registers:
**********************************************************************/
/***********************************************************************
* Channel Registers: R_RSTC: Receive RST Configuration
* Page - (1cc)80H
**********************************************************************/
#define ixf6048_R_RSTC_CHAN_OFFSET(Chan) \
(((1<<10)+(0x80)+(Chan<<8))<<REG_SHIFT)
#define ixf6048_mNO_FORCE_R_RSTC 0xFFFF
#define ixf6048_bRCV_SCRMBL_CNFG 0x8000 /* Enable Receive Scrambler 2e7 */
#define ixf6048_bRCV_F_BA_DSBL 0x4000 /* Use RFPI Pulse */
#define ixf6048_bRCV_FWD_OFF_CNFG 0x2000 /* Bit 13 */
#define ixf6048_bRCV_FWD_ON_CNFG 0x1000 /* Bit 12 */
#define ixf6048_bCNFG_B1_CNTR 0x0800 /* 1 = Cnt B1 Blk errs
0 = Cnt Bit Errors */
#define ixf6048_bRST_CLK_LOCKN 0x0100
#define ixf6048_bRST_AIS_LOFN 0x0080
#define ixf6048_bRST_AIS_LOSN 0x0040
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