ixf6048b.h

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

#define  ixf6048_bLINE_LOOP_BACK   0x0008   /* Enable Line Loopback   */

#define  ixf6048_bCH_ENA          0x0004   /* Enable Channel traffic */

/* */
#define  ixf6048_mCHAN_RATE       0x0003   /* Mask for Chan Rate bits */
#define  ixf6048_bCHAN_RATE_OC48  0x0003   /* Chan rate = OC-48 (Single Chan - Chan 0)*/
#define  ixf6048_bCHAN_RATE_OC12  0x0002   /* Chan rate = OC-12           */
#define  ixf6048_bCHAN_RATE_OC3   0x0001   /* Chan rate = OC-3            */
#define  ixf6048_bCHAN_RATE_OC1   0x0000   /* Chan rate = OC-1            */


/***********************************************************************
 * Channel Registers: R_COCNF: Rx Channel Operational Configuration
 * Page 195-6 - (0cc)0AH
 **********************************************************************/

#define  ixf6048_R_COCNF_CHAN_OFFSET(Chan)    \
                     (((0x0A)+(Chan<<8)) << REG_SHIFT) /* Byte Offset of register */

/* PSN_ADDED Added for B1 Release Software */
#define  ixf6048_bRCV_TRANS_DESCR_EN     0x0200
/* PSN_END B1 Release Changes */
#define  ixf6048_bRCV_LOCK_CNF        0x0100 /* For RLOCK_i to be Active High */
#define  ixf6048_mCO_CNF              0x00E0 
     /* Convert ixf6048_RxTtlClockDivide_e to bits */
#define  ixf6048_SET_CO_CNF(Reg, ClkDiv)   \
                     (Reg |= ( (Reg & ~ixf6048_mCO_CNF      ) |  \
                                  ((ClkDiv << 5) & ixf6048_mCO_CNF) ) )
#define  ixf6048_RCV_CO_CNF_TTL_CLK_DIV(ClkDiv) ((ClkDiv-1)<<5)/* RX COCNF TTL Clock */
/* See ixf6048_RxLineSideInterface_e for Bit Definitions of IfMode*/
#define  ixf6048_mIF_MODE              (0x0007<<2)
#define  ixf6048_GET_IF_MODE(Reg)       \
                     ((Reg & ixf6048_mIF_MODE) >> 2)
/* Convert ixf6048_RxLineSideInterface_e to Bit Values*/
#define  ixf6048_SET_IF_MODE(Reg,IfMode)   \
                     (Reg |= ( (Reg & ~ixf6048_mIF_MODE    ) | \
                                  ((IfMode<< 2)& ixf6048_mIF_MODE) ) )

/* the bit for the corresponding IF Mode */
#define  ixf6048_bIF_MODE(IfMode) (IfMode<< 2)

#define  ixf6048_mCHAN_MODE             0x0003 /* Mask the Chanel Mode */
#define  ixf6048_bCHAN_MODE_POS         0x0003 /* Chan Mode = POS        */
#define  ixf6048_bCHAN_MODE_ATM         0x0002 /* Chan Mode = ATM          */
#define  ixf6048_bCHAN_MODE_TRANSPARENT 0x0001 /* Chan Mode = Transparent*/
#define  ixf6048_bCHAN_MODE_TEST        0x0000 /* Chan Mode = Repeater   */

/***********************************************************************
 * Channel Registers: T_COCNF: Tx Channel Operational Configuration
 * Page  - (0cc)0BH
 **********************************************************************/

#define  ixf6048_T_COCNF_CHAN_OFFSET(Chan)  \
               (((0x0B)+(Chan<<8)) << REG_SHIFT) /* Byte Offset of register */

/* PSN_ADDED Added for B1 Release Software */
#define  ixf6048_bXMT_TRANS_SCR_EN      0x0800               
/* PSN_END B1 Release Changes */
#define  ixf6048_bXMT_PCLK_OUT          0x0400 /* |= to Disable PECL out clk */

/* Convert ixf6048_TxTimingSource_e to bits */
#define  ixf6048_mXMT_TIM_REF           (0x03<<8)
#define  ixf6048_SET_XMT_TIM_REF_CLK_SRC(Reg, ClkSrc) \
                     (Reg |= ( (Reg & ~ixf6048_mXMT_TIM_REF    ) | \
                                  ((ClkSrc<< 8)& ixf6048_mXMT_TIM_REF) ) )

#define  ixf6048_XMT_TIM_REF_CLK_SRC(ClkSrc) \
         (ClkSrc<<8)      /* Convert ixf6048_TxTimingSource_e to bits */

#define  ixf6048_XMT_CO_CNF_TTL_CLK_DIV(ClkDiv)   \
         ((ClkDiv-1)<<5)      /* Convert ixf6048_TxTtlClockDivide_e to bits */
/* See ixf6048_TxLineSideInterface_e for Bit Definitions of IfMode */
/* Notes: CO_CNF Clock Source Defined in Reg R_COCNF above
          IF_MODE N-Bit TTL or PCL Defined in Reg R_COCNF above
          Chan Modes Defined in Reg R_COCNF above  */

/***********************************************************************
 * Global Registers: OHPCNF: Overhead Ports Configuration
 * Page  - (000)0CH
 **********************************************************************/
#define  ixf6048_OHPCNF_OFFSET (0x0C << REG_SHIFT) /* Byte Offset of register */

#define  ixf6048_bOW_PlS_CNF      0x0002   /* for Location of Pulse Byte */
#define  ixf6048_bOH_PORT_MODE    0x0001   /* Set for DCC & Orderwire 
                                             Insertion/extraction Ports Quad 
                                             PHY Mode                   */
/***********************************************************************
 * Global Registers: R_FPCNF: Rx Frame Pulse Configuration
 * Page  - (000)0DH
 **********************************************************************/
#define  ixf6048_R_FPCNF_OFFSET (0x0D << REG_SHIFT)

#define  ixf6048_mRCV_FPI_CNF         0x00FF   /* Receive Input frame Pulse */

/***********************************************************************
 * Global Registers: T_FPCNF: Tx Frame Pulse Configuration
 * Page  - (000)0EH
 **********************************************************************/

#define  ixf6048_T_FPCNF_OFFSET (0x0E << REG_SHIFT) 

#define  ixf6048_XMT_FPO_CNF_MASK     0xFF00   /* Mask for value */
#define  ixf6048_XMT_FPI_CNF_MASK     0x00FF   /* Mask for value */

#define  SET_XMT_FRAME_PULSE_CNF(Reg, fpo, fpi)   \
            (Reg = (((fpo << 8) & ixf6048_XMT_FPO_CNF_MASK) | \
                    (fpi &ixf6048_XMT_FPI_CNF_MASK) ) )
/***********************************************************************
 * Global Registers: OCPCNF: Output Clock Polarity Configuration
 * Page  - (000)0FH
 **********************************************************************/

#define  ixf6048_OCPCNF_OFFSET (0x0F << REG_SHIFT) 

#define  ixf6048_mOCPCNF    0xFFFD   /* Mask for Register */

/* See ixf6048_OutClockPolarity_e for bits*/

/***********************************************************************
 * Global Registers: ICPCNF1: Input Clock Polarity Configuration 1
 * Page  - (000)10H
 **********************************************************************/

#define  ixf6048_ICPCNF1_OFFSET (0x10 << REG_SHIFT)

/* Note: see ixf6048_InClockPolarity1_e for bits*/
/***********************************************************************
 * Global Registers: ICPCNF2: Input Clock Polarity Configuration 2
 * Page  - (000)11H
 **********************************************************************/

#define  ixf6048_ICPCNF2_OFFSET (0x11 << REG_SHIFT) 

#define  ixf6048_OCPCNF2_MASK     0x0003   /* Mask for value */

/* Note: See ixf6048_InClockPolarity2_e for bits */
/***********************************************************************
 * Global Registers: ICMR1: Input Clock Monitoring Reg
 * Page  - (000)12H
 **********************************************************************/
#define  ixf6048_ICMR1_OFFSET (0x12 << REG_SHIFT)

#define  ixf6048_eCHG_TCI_T3_INVERTED	0x8000
#define  ixf6048_eCHG_TCI_T2_INVERTED	0x4000
#define  ixf6048_eCHG_TCI_T1_INVERTED	0x2000
#define  ixf6048_eCHG_TCI_T0_INVERTED	0x1000

#define  ixf6048_eCHG_RCI_T3_INVERTED	0x0800
#define  ixf6048_eCHG_RCI_T2_INVERTED	0x0400
#define  ixf6048_eCHG_RCI_T1_INVERTED	0x0200
#define  ixf6048_eCHG_RCI_T0_INVERTED	0x0100

#define  ixf6048_eCHG_TSCI_P3_INVERTED	0x0080
#define  ixf6048_eCHG_TSCI_P2_INVERTED	0x0040
#define  ixf6048_eCHG_TSCI_P1_INVERTED	0x0020
#define  ixf6048_eCHG_TSCI_P0_INVERTED	0x0010

#define  ixf6048_eCHG_RSCI_P3_INVERTED	0x0008
#define  ixf6048_eCHG_RSCI_P2_INVERTED	0x0004
#define  ixf6048_eCHG_RSCI_P1_INVERTED	0x0002
#define  ixf6048_eCHG_RSCI_P0_INVERTED	0x0001


/* Note: See ixf6048_InClockMonitor1_e */
/***********************************************************************
 * Global Registers: ICMR2: Input Clock Monitoring Reg
 * Page  - (000)13H
 **********************************************************************/
#define  ixf6048_ICMR2_OFFSET (0x13 << REG_SHIFT) 

#define  ixf6048_mICMR2       0xFF03   /* Mask for value */
#define ixf6048_eCHG_TXCLK_3_INVERTED	0x8000
#define ixf6048_eCHG_TXCLK_2_INVERTED	0x4000
#define ixf6048_eCHG_TXCLK_1_INVERTED	0x2000
#define ixf6048_eCHG_TXCLK_0_INVERTED	0x1000

#define	ixf6048_eCHG_RXCLK_3_INVERTED	0x0800
#define	ixf6048_eCHG_RXCLK_2_INVERTED	0x0400
#define	ixf6048_eCHG_RXCLK_1_INVERTED	0x0200
#define	ixf6048_eCHG_RXCLK_0_INVERTED	0x0100

#define	ixf6048_eCHG_TPCI_P_INVERTED	0x0002
#define	ixf6048_eCHG_RPCI_P_INVERTED	0x0001


/* Note: See ixf6048_InClockMonitor2_e */
/***********************************************************************
 * Global Registers: NCMODECNF: Non-concatenated mode Coniguration register
 * Page  - (000)14H
 **********************************************************************/

#define  ixf6048_NCMODECNF_OFFSET (0x14 << REG_SHIFT)

#define  ixf6048_mNCMODECNF        0x001F   /* Mask for value */
#define  ixf6048_bJ0_MUX_CNF       0x0010   /* C0 Bytes are Overwritten */
#define  ixf6048_bRES_M1_MUX_CNF   0x0008   /* Reserved for Level One Communications(tm) Testing*/
#define  ixf6048_bB_W_MUX_CNF      0x0004   /* Byte Interleaved Mux      */
#define  ixf6048_bRES_M1_DMX_CNF   0x0002   /* Reserved for Level One Communications(tm) Testing */
#define  ixf6048_bB_W_DMX_CNF      0x0001   /* Byte Interleaved De-Mux   */

/***********************************************************************
 * Global Registers: TESTCNF: Test Configuration register
 * Page  - (000)15H
 **********************************************************************/

#define  ixf6048_TESTCNF_OFFSET (0x15 << REG_SHIFT)

/* NOTE: The User Must write a 0 to all of the following Bits */
#define  ixf6048_TESTCNF_MASK        0x003F   /* use ClrBits macro with Mask*/
/***********************************************************************
 * Global Registers: TESTRAM_0: Test RAM register
 * Page  - (000)16H
 **********************************************************************/
/* Note: This Register is Reserved for Level One Communication Use Only */
#define  ixf6048_TESTRAM_0_OFFSET (0x16 << REG_SHIFT)

/***********************************************************************
 * Global Registers: TESTRAM_1: Test RAM register
 * Page  - (000)17H
 **********************************************************************/
/* Note: This Register is Reserved for Level One Communication Use Only */
#define  ixf6048_TESTRAM_1_OFFSET (0x17 << REG_SHIFT)

 /***********************************************************************
 * Global Registers: TESTRAM_2: Test RAM register
 * Page  - (000)18H
 **********************************************************************/
/* Note: This Register is Reserved for Level One Communication Use Only */
#define  ixf6048_TESTRAM_2_OFFSET (0x18 << REG_SHIFT)

/***********************************************************************
 * Global Registers: TESTRAM_3: Test RAM register
 * Page  - (000)19H
 **********************************************************************/
/* Note: This Register is Reserved for Level One Communication Use Only */
#define  ixf6048_TESTRAM_3_OFFSET (0x19 << REG_SHIFT)

/***********************************************************************
 * Global Registers: PRBSINT: PRBS Analyze Interupt register
 * Page  - (000)1AH
 **********************************************************************/

#define  ixf6048_PRBSINT_OFFSET (0x1A << REG_SHIFT)

#define  ixf6048_bPRBSI(Chan) (0x0001<<Chan) /* Read Only  */
/***********************************************************************
 * Global Registers: PRBSINTEN: PRBS Analyze Interupt Enable register
 * Page  - (000)1BH
 **********************************************************************/
#define  ixf6048_PRBSINTEN_OFFSET (0x1B << REG_SHIFT)

#define  ixf6048_bPRBSINTEN(Chan) (0x0001<<Chan)  

/* See  ixf6048_PRBSINT_OFFSET for Masks */
/***********************************************************************
 * Global Registers: TALBINT: Tx Alarm Bus Interupt register
 * Page  - (000)H
 **********************************************************************/
#define  ixf6048_TALBINT_OFFSET (0x1C << REG_SHIFT)

#define  ixf6048_mTALB_INT    0xFFFF   /* Mask for All Interupt Bits */

#define  ixf6048_TPAL_CRCI_CHAN3	0x8000
#define  ixf6048_TPAL_CRCI_CHAN2	0x4000
#define  ixf6048_TPAL_CRCI_CHAN1	0x2000
#define  ixf6048_TPAL_CRCI_CHAN0	0x1000

#define  ixf6048_TPAL_BUSI_CHAN3	0x0800
#define  ixf6048_TPAL_BUSI_CHAN2	0x0400
#define  ixf6048_TPAL_BUSI_CHAN1	0x0200
#define  ixf6048_TPAL_BUSI_CHAN0	0x0100


#define  ixf6048_TSAL_CRCI_CHAN3	0x0080
#define  ixf6048_TSAL_CRCI_CHAN2	0x0040
#define  ixf6048_TSAL_CRCI_CHAN1	0x0020
#define  ixf6048_TSAL_CRCI_CHAN0	0x0010

#define  ixf6048_TSAL_BUSI_CHAN3	0x0008
#define  ixf6048_TSAL_BUSI_CHAN2	0x0004
#define  ixf6048_TSAL_BUSI_CHAN1	0x0002
#define  ixf6048_TSAL_BUSI_CHAN0	0x0001

/***********************************************************************
 * Global Registers: TALBINTEN: Tx Alarm Bus Interupt Enable register
 * Page  - (000)H
 **********************************************************************/
#define  ixf6048_TALBINTEN_OFFSET (0x1D << REG_SHIFT)

#define  ixf6048_GET_TALBINTEN_CHAN_INT_MASK(Chan) (0x1111 << Chan)
/***********************************************************************