ixf6048b.h

开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测

/*
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2001 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *   AUTHOR:         $Author: lagarwal $
 *   DATE:           $Date: 2003/07/29 21:25:10 $
 *   LAST MODIFIED:  $Modtime: 5/17/02 1:58p $
 *   REV#:           $Revision: 1.2 $
 *   LOGFILE:        $Logfile: /Embedded/source/drivers/ixf/ixf6048/ixf6048.c $
 *   WORKFILE:       $Workfile: bkcompat.c $
 *
 * --------------------------------------------------------------------------
 * Project: IXF6048
 *
 * Purpose: IXF6048 bits & functions - used only by the driver
 *			
 * Notes: Only the values required by the Driver are defined.
 *    Note that addresses in the Data Sheet are referenced to 16-bit words,
 *    and in fact are word addresses. Depending on your compiler and your
 *	  uP, it may be necessary to double the Register offsets
 * 	  in order to Generate the correct 16-bit aligned addresses. 
 * 		- Some Compilers will automatically double these offset, while 
 *		  others will require that the author double the values.
 *      - Some uP's do Not support odd addresses for 16-Bit accesses.
 *    To Resolve these issues and others, the constant:
 *				REG_SHIFT
 *	  has been included in the Address Macro, and should be Defined as 
 *    a value of 0 or 1 depending on your Addressing requirements.
 *
 *    Note that only 16-bit accesses are supported by the registers.
 *			
 * --------------------------------------------------------------------------
 * CompilerFlags: 
 * --------------------------------------------------------------------------
 * --------------------------------------------------------------------------
 *   $Log: ixf6048b.h,v $
 *   Revision 1.2  2003/07/29 21:25:10  lagarwal
 *   no message
 *
 *   Revision 1.1.1.1  2002/11/15 17:51:11  lagarwal
 *   rename dir
 *
 *   Revision 1.6  2002/10/31 19:03:23  machambe
 *   no message
 *
 *   Revision 1.2  2002/10/27 18:21:36  machambe
 *   no message
 *
 * --------------------------------------------------------------------------
 */ 
#ifndef BB6048B_H_ /* Include file contents only once per compilation */
#define BB6048B_H_

/* See Comment in File header above */
#define REG_SHIFT 0

/*Get Shift Bit Macro*/
#define	ixf6048_GET_SHIFT_BIT(StartBit, Shift)   (StartBit<<Shift)

/* Bit Shifts */
#define ixf6048_BIT_SHIFT_0	0
#define ixf6048_BIT_SHIFT_1	1
#define ixf6048_BIT_SHIFT_2	2
#define ixf6048_BIT_SHIFT_3	3
#define ixf6048_BIT_SHIFT_4	4
#define ixf6048_BIT_SHIFT_5	5
#define ixf6048_BIT_SHIFT_6	6
#define ixf6048_BIT_SHIFT_7	7
#define ixf6048_BIT_SHIFT_8	8
#define ixf6048_BIT_SHIFT_9	9
#define ixf6048_BIT_SHIFT_10	10
#define ixf6048_BIT_SHIFT_11	11
#define ixf6048_BIT_SHIFT_12	12
#define ixf6048_BIT_SHIFT_13	13
#define ixf6048_BIT_SHIFT_14	14
#define ixf6048_BIT_SHIFT_15	15

/* Default register Value of 0 */
#define ixf6048_ZERO_DFLT 0

/***********************************************************************
 * Global Registers: MACNF: Microprocessor Access Config Reg
 * Page 186 - (000)01H
 **********************************************************************/

#define  ixf6048_MACNF_OFFSET (0x01 << REG_SHIFT) /* Byte Offset of register */

#define  ixf6048_bBYTE_CHG_UPD_DSBL  0x0004  /* Set to Disable receive Byte 
                                            Regster Updates when Byte change
                                            interupt is active. Default= 0 */
#define  ixf6048_bCNTR_TEST_EN    0x0002     /* Set to force counter overflow */
                                            /* on B1 bit & Bit/Blk for B2,
                                               M1 REI, B3, B1 REI Counters */
#define  ixf6048_bMAS_INT_EN      0x0001     /* Set to enable chip interrupts */

/***********************************************************************
 * Global Registers: CHIP_ID: Chip ID & Version Number
 * Page 186 - (000)02H
 **********************************************************************/

#define  ixf6048_CHIP_ID_OFFSET (0x02 << REG_SHIFT) /* Byte Offset of register */

#define  ixf6048_mCHIP_VER      0xFF00   /* MSB Mask for Chip Version */
#define  ixf6048_mCHIP_ID       0x00FF   /* LSB Mask for Chip ID */

/***********************************************************************
 * Global Registers: SRESET: Software Reset Register
 * Reg  - (000)03H
 * Set (Writing 1 bit) => held in reset
 * Clr (Writing 0 bit) => comes out of reset
 * Note: Even if bit was set (& chip/channel held in reset) it will read back 0
 * Note: To clear a reset for a bit, write 0x0000 to register.
 **********************************************************************/

#define  ixf6048_SW_RESET_OFFSET (0x03 << REG_SHIFT) /* Byte Offset of register */

#define  ixf6048_bSW_RESET_CHIP      0x0100 /* Reset entire Amazon chip */

/* Set or clear the reset transmit channel reset register. */
/* Note: SetClr Must be 0 or 1                             */
#define  ixf6048_RESET_XMT_CH(BaseAddress, Chan, SetClr)   \
             (WRITE_TO_HW(BaseAddress + ixf6048_SW_RESET_OFFSET,   \
                  ( (0x0010 << (Chan)  ) &  \
                    (SetClr << (Chan+4)) ) ) )

#define  ixf6048_bRESET_XMT_CH(Chan, SetClr) ((0x0010<<(Chan)) &  \
                                                (SetClr << (Chan+4)) )

#define  ixf6048_RESET_RCV_CH(BaseAddress, Chan, SetClr)   \
             (WRITE_TO_HW(BaseAddress + ixf6048_SW_RESET_OFFSET,   \
                  ( (0x0001<<(Chan) ) &  \
                    (SetClr << Chan ) ) ) )

#define  ixf6048_bRESET_RCV_CH(Chan, SetClr) ((0x0001<<(Chan)) &  \
                                                (SetClr << (Chan)) )

#define  ixf6048_RESET_CHANNEL(BaseAddress, Chan, SetClr)   \
             (WRITE_TO_HW(BaseAddress + ixf6048_SW_RESET_OFFSET,   \
                  ( (0x0011<<(Chan) ) &  \
                    ((SetClr << Chan )|(SetClr << (Chan+4)) ) ) ) )

/***********************************************************************
 * Global Registers: BUF_ACNTS: Buffer all counters -- Page 188 - (000)04H
 **********************************************************************/

#define  ixf6048_BUF_ACNTS_OFFSET (0x04 << REG_SHIFT)

         /* Chan = 0-3 below */
/* Mask to Buffer all OHT Rx Counters for channel. Tx is Unused */
#define  ixf6048_MASK_OHT_CHAN_CNTRS(Chan) \
            (0x1100 << Chan)     
/* Mask to Buffer all ATM/POS Rx,Tx Counters for chan */
#define  ixf6048_MASK_ATM_POS_CHAN_CNTRS(Chan)   \
         (0x0011 << Chan)     
/* Mask to Buffer all ATM/POS Rx Counters for chan */
#define  ixf6048_MASK_ATM_POS_RX_CHAN_CNTRS(Chan)   \
         (0x0001 << Chan)     
/* Mask to Buffer all ATM/POS Tx Counters for chan */
#define  ixf6048_MASK_ATM_POS_TX_CHAN_CNTRS(Chan)   \
         (0x0010 << Chan)     

/* Buffer the counters defined by "Mask" */
#define  ixf6048_BUFFER_COUNTERS(BaseAddress, ChanMask) \
            ((WRITE_TO_HW(BaseAddress + ixf6048_BUF_ACNTS_OFFSET, ChanMask)))
/***********************************************************************
 * Global Registers: SDH_GIS: SDH Global Interrupt Source
 * Page 189 - (000)05H
 *
 * Use:
 * 1) If any of 16-bits in reg not = 0, then => SDH interrupt(s) to handle
 * 2) Check each channel 0-3 for active SDH interrupt, if so:
 *    3) Check (masked bits for 1 channel) against type of interrupt:
 *       namely: Rx RST, Rx MST, Rx MSA, Rx HPT.
 **********************************************************************/

#define  ixf6048_SDH_GIS_OFFSET (0x05 << REG_SHIFT) 

#define  ixf6048_SDH_CHAN_INT(Chan) \
         (0x1111 << Chan)     /* to see if any interrupt for specific chan */

#define  ixf6048_RX_HPT_INT   0xF000   /* Test for Rx HPT int for any chan */
#define  ixf6048_RX_ADP_INT   0x0F00   /* Test for Rx MSA int for any chan */
#define  ixf6048_RX_MUX_INT   0x00F0   /* Test for Rx MST int for any chan */
#define  ixf6048_RX_REG_INT   0x000F   /* Test for Rx RG  int for any chan */

/***********************************************************************
 * Global Registers: ATMPOS_GIS: ATM & POS Global Interrupt Source
 * Page  - (000)06H
 *
 * Use:
 * 1) If any of 16-bits in reg not = 0, then => ATM or POS int(s) to handle
 * 2) Check each channel 0-3 for active ATM/POS interrupt, if so:
 *    3) Check (masked bits for 1 channel) against type of interrupt:
 *       namely: Rx ATM or Tx ATM (if ATM chan)
 *               Rx POS or Tx POS (if POS chan)
 **********************************************************************/

#define  ixf6048_ATMPOS_GIS_OFFSET (0x06 << REG_SHIFT) 

#define  ixf6048_ATM_CHAN_INT(Chan) \
         (0x1100 << Chan)     /* to see if ATM interrupt for specific chan */

#define  ixf6048_POS_CHAN_INT(Chan) \
         (0x0011 << Chan)     /* to see if POS interrupt for specific chan */

#define  ixf6048_TX_ATM_INT   0xF000   /* Test for Tx ATM int for any chan */
#define  ixf6048_RX_ATM_INT   0x0F00   /* Test for Rx ATM int for any chan */
#define  ixf6048_TX_POS_INT   0x00F0   /* Test for Tx POS int for any chan */
#define  ixf6048_RX_POS_INT   0x000F   /* Test for Rx POS int for any chan */

/***********************************************************************
 * Global Registers: S_AIS: SDH/SONET Rx AIS
 * Page 190 - (000)07H
 * This Register is primarily used for Testing purposes. It indicates the
 * internal status of the internal chip logic for AIS generation Processes.
 **********************************************************************/

#define  ixf6048_S_AIS_OFFSET (0x07 << REG_SHIFT) 

#define  ixf6048_GEN_S_AIS_ST(Chan) \
         (0x1111 << Chan)     /*Present Status of AIS generator */

#define  ixf6048_GEN_RST_AIS_ST 0xF000  /* Mask Status of RST AIS generator */
#define  ixf6048_GEN_MST_AIS_ST 0x0F00  /* Mask Status of MST AIS generator */
#define  ixf6048_GEN_MSA_AIS_ST 0x00F0  /* Mask Status of MSA AIS generator */
#define  ixf6048_GEN_HPT_AIS_ST 0x000F  /* Mask Status of HPT AIS generator */
/***********************************************************************
 * Global Registers: GOCNF: Global Operational Configuration
 * Page 191 - (000)08H
 * This Register configures AMAZON-A global configuration features.
 **********************************************************************/

#define  ixf6048_GOCNF_OFFSET (0x08 << REG_SHIFT) 

/* PSN_ADDED B1 Release Changes */
#define  ixf6048_bGEN_IO_VAL         0x2000
#define  ixf6048_bGEN_IO_MODE        0x1000
#define  ixf6048_bRCV_U_OUT_EN_CNF   0x0800
#define  ixf6048_bXMT_U_OUT_EN_CNF   0x0400
#define  ixf6048_bXMT_PECL_MSB_CNF   0x0200
#define  ixf6048_bRCV_PECL_MSB_CNF   0x0100
#define  ixf6048_UTOPIA_OUT_ENABLE	 0x0010
#define  ixf6048_AMAZON_OUT_ENABLE   0x0008
/* PSN_END B1 Release Changes */

#define  ixf6048_bU64_MODE     0x0080  /* Configure UTOPIA Interface to 64 Bit Mode */

#define  ixf6048_bQUAD_MODE    0x0040  /* Line Side = Quad Channel Mode */

#define  ixf6048_bC_MODE       0x0020  /* Set => Line Side = Concatenated Mode */
                                    /* Note: Only used if Single Chan Mode */

                                    /* UTOPIA & I/O bus Outputs En/Disabled */
#define  ixf6048_CHIP_ENABLE    0x0018/* |= to Set => Enabled */
#define  ixf6048_CHIP_DISABLE   0xFFE7/* &= to Clr => Disabled */

                                    /* Note: Masked value cannot = 0x7 */
#define  ixf6048_mUTOPIA_ADDR_BASE 0x0007   /* Mask for UTOPIA Addr Base */


/***********************************************************************
 * Channel Registers: COCNF: Channel Operational Configuration
 * Page 193 - (0cc)09H
 **********************************************************************/

#define  ixf6048_COCNF_CHAN_OFFSET(Chan)  \
         (((0x09)+(Chan<<8)) << REG_SHIFT)

#define  ixf6048_bCHAN_REPEATER_MODE  0x0020   /* Chan Mode = Repeater  */

#define  ixf6048_bCHAN_SYS_LOOPBACK   0x0010   /* Enable Local Loopback    */

  /* This requires that the Rx and Tx Line Side interfaces are the same: 
     namely RxLineSideInterface = TxLineSideInterface in MuxChanIfConfig */