📄 bdwcommon.c
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/*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2001 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*/
#include "common_types.h"
#include "common_def.h"
#include "common.h"
#include "ixf_api_d.h"
#include "ixf_api.h"
#include "diagstruct.h"
#include "bdw.h"
#include "bdwcommon.h"
#include "misc_func.h"
#include "hal_ixdp2400.h"
#include "syslog.h"
#include "i2c.h"
#define CHKSUM 0x0000
#define DATE 0x0000
#define DEVID 0x0000
#define MANID 0x0000
#define MODEL 0x0000
#define PARTID 0x0000
#define PARTID 0x0000
#define PASSWD 0x0000
#define PROMFMT 0x0000
char* Get_CPU(void);
int Get_CPU_Speed(void);
int Get_CPU_Rev(void);
int Get_SRAM_Size(void);
int Get_SDRAM_Size(void);
int Get_Host_Type(void);
extern UINT32 sram_size[2];
void DiagStructInit(void *chipId)
{
register eduCommon* acL = (eduCommon *) ACADDRESS;
//Setup the Diag common structure with default values.
acL->dc.tFlag[TFLAG_SRAM] = 1;
acL->dc.tFlag[TFLAG_SDRAM] = 1; /* do the T ALL SDRAM test */
acL->dc.tFlag[TFLAG_UENG] = 1; /* do the T ALL UENG test */
acL->dc.tFlag[TFLAG_TIMERS] = 1; /* do the T ALL TIMERS test */
acL->dc.tFlag[TFLAG_ENET] = 1; /* do the T ALL ENET test */
acL->dc.tFlag[TFLAG_PCI] = 1; /* do the T ALL PCI test */
acL->dc.tFlag[TFLAG_XSCALE] = 1; /* do the T ALL XSCALE test */
acL->dc.tFlag[TFLAG_I2C] = 0;
acL->dc.tFlag[TFLAG_GPIO] = 0;
acL->dc.tFlag[TFLAG_LED] = 1; /* do the T ALL LED test */
acL->dc.tFlag[TFLAG_UART] = 0; /* do the T ALL UART test */
acL->dc.tFlag[TFLAG_SF] = 0; /* do the T ALL SF test */
acL->dc.tFlag[TFLAG_LOOPBACK] = 0; /* do the T ALL LOOPBACK test */
acL->dc.tFlag[TFLAG_TMON] = 0;
acL->dc.tFlag[TFLAG_FLASH] = 0;
acL->dc.tFlag[TFLAG_LINERATE] = 0;
acL->dc.targetName = (char*) "Battery Drew/Wallace";
acL->dc.targetCpu = (char*) "IXP2400";
acL->dc.SDRAMSize = Get_SDRAM_Size();
acL->dc.SRAMSize = Get_SRAM_Size();
acL->dc.CPURevision = Get_CPU_Rev();/* set revision before speed! */
acL->dc.CPUSpeed = Get_CPU_Speed();
acL->dc.HostType = Get_Host_Type(); // Master/Slave
acL->dc.UStoreSize = 4096;
acL->dc.defAddress = 0; /* no default address yet */
acL->dc.Verboselevel = LOG_OFF;
acL->dc.HaltOnError = ENABLED;
acL->dc.Err = OK;
/* PRBS data */
acL->prbsChanNum = 0; /* PRBS channel number */
acL->chipId = chipId;
}
void
GetI2CData(I2Cstruct_t *data)
{
/* Clear data */
bzero((volatile char *) data, (ulong) sizeof(I2Cstruct_t));
i2c_seq_read(SLAVE_ADDR_2,0x0, (unsigned char *)data, sizeof(struct MEDIA_EEPROM_CONTENT));
}
void
ResetDeviceToKnownState(bb_ChipData_t *pChipData, const InitRegTable_t *pTable)
{
bb_ChipSegment_t section;
/* Initialize the channel */
section.group.channel = 0;
/* Reset ixf6048*/
IxfApiReset(pChipData, §ion, bb_RESET_CHIP);
/* Initialize chip to a known state */
IxfApiInitChip(pChipData, (InitRegTable_t *) pTable);
}
//
// Function: Get_CPU
//
// Description: Reads PRODUCT_ID register to obtain CPU Product Type
//
char* Get_CPU(void)
{
switch( (GET32(GLOBAL_CONTROL_BASE) >> 8) & 0xFF)
{
case 0: return("IXP2800");
case 1: return("IXP2800 with Crypto");
case 2: return("IXP2400");
default: return("Unknown NPU");
}
}
//
// Function: Get_CPU_Speed
//
// Description: Reads M_CLK and N_CLK and calculate CPU Speed
//
int Get_CPU_Speed(void)
{
// This function will return the speed of NPU in Hz.
int M_clk = 0;
int N_clk, temp;
int denom_array[] = {2, 4, 8, 16, 1, 2, 4, 8};
if(((GET32(CPLD_REV_REG)>>4) & 0xF) >= 4) // if board rev is 4 and up
{
temp = *(SYS_CLK_M_REG);
M_clk = (temp & (0xFF)) * 2;
temp = *(SYS_CLK_N_REG);
N_clk = denom_array[(temp & 0x7)];
temp = 6 * ((3125000 * M_clk)/N_clk); // in Hz
}
else
temp = (600 * 1000000); // in hz
return (temp);
}
//
// Function: Get_CPU_Rev
//
// Description: Reads PRODUCT_ID register to obtain the CPU Rev
//
int Get_CPU_Rev(void)
{
// This function will return the NPU revision.
// It will read the PRODUCT_ID register and return the value to caller.
// PRODUCT_ID's offset is zero from GLOBAL_CONTROL_BASE
int cpu_rev = 0xFF & GET32(GLOBAL_CONTROL_BASE);
return (cpu_rev);
}
//
// Function: Get_SRAM_size
//
// Description: grabs the sram size from BIC
//
int Get_SRAM_Size(void)
{
return (sram_size[0] + sram_size[1]);
}
//
// Function: Get_SDRAM_size
//
// Description: Reads number of module rows and density of each row on module
// from the DRAM I2C PROM. Then, calculates the size of DRAM.
//
int Get_SDRAM_Size(void)
{
extern UINT32 hal_dram_size; // calculated in BIC and stored
return (hal_dram_size);
}
//
// Function: Get_Host_Type
//
// Description: Determines if current NPU is master or slave
//
int Get_Host_Type(void)
{
if(GET32(STRAP_OPTIONS) & CFG_PCI_BOOT_HOST) // if master NPU
return MASTER;
else
return SLAVE;
}
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