📄 hal_diag.c
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/*=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####COPYRIGHTBEGIN####
//
// -------------------------------------------
// The contents of this file are subject to the Red Hat eCos Public License
// Version 1.1 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://www.redhat.com/
//
// Software distributed under the License is distributed on an "AS IS"
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
// License for the specific language governing rights and limitations under
// the License.
//
// The Original Code is eCos - Embedded Configurable Operating System,
// released September 30, 1998.
//
// The Initial Developer of the Original Code is Red Hat.
// Portions created by Red Hat are
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
// All Rights Reserved.
// -------------------------------------------
//
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): msalter
// Contributors:msalter
// Date: 2000-10-10
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/hal/hal_arch.h> // basic machine info
#include <cyg/hal/hal_intr.h> // interrupt macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // calling interface API
#include <cyg/hal/hal_misc.h> // helper functions
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_iq80310.h> // Hardware definitions
#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
static void cyg_hal_plf_serial_init(void);
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
if (initialized)
return;
initialized = 1;
cyg_hal_plf_serial_init();
// cyg_hal_plf_lcd_init();
}
//=============================================================================
// Serial driver
//=============================================================================
//-----------------------------------------------------------------------------
// There are two serial ports.
#define CYG_DEV_SERIAL_BASE_A 0xfe800000 // port A
#define CYG_DEV_SERIAL_BASE_B 0xfe810000 // port B
//-----------------------------------------------------------------------------
// Default baud rate is 38400
// Based on 3.6864 MHz xtal
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
#define CYG_DEV_SERIAL_BAUD_MSB 0x00
#define CYG_DEV_SERIAL_BAUD_LSB 0x0c
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
#define CYG_DEV_SERIAL_BAUD_MSB 0x00
#define CYG_DEV_SERIAL_BAUD_LSB 0x06
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
#define CYG_DEV_SERIAL_BAUD_MSB 0x00
#define CYG_DEV_SERIAL_BAUD_LSB 0x03
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
#define CYG_DEV_SERIAL_BAUD_MSB 0x00
#define CYG_DEV_SERIAL_BAUD_LSB 0x02
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
#define CYG_DEV_SERIAL_BAUD_MSB 0x00
#define CYG_DEV_SERIAL_BAUD_LSB 0x01
#endif
#ifndef CYG_DEV_SERIAL_BAUD_MSB
#error Missing/incorrect serial baud rate defined - CDL error?
#endif
//-----------------------------------------------------------------------------
// Define the serial registers. The Cogent board is equipped with a 16552
// serial chip.
#define CYG_DEV_SERIAL_RBR 0x00 // receiver buffer register, read, dlab = 0
#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
#define CYG_DEV_SERIAL_LCR 0x03 // line control register, write
#define CYG_DEV_SERIAL_MCR 0x04 // modem control register, write
#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
// The interrupt enable register bits.
#define SIO_IER_ERDAI 0x01 // enable received data available irq
#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
#define SIO_IER_ELSI 0x04 // enable receiver line status irq
#define SIO_IER_EMSI 0x08 // enable modem status interrupt
// The interrupt identification register bits.
#define SIO_IIR_IP 0x01 // 0 if interrupt pending
#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
#define ISR_Tx 0x02
#define ISR_Rx 0x04
// The line status register bits.
#define SIO_LSR_DR 0x01 // data ready
#define SIO_LSR_OE 0x02 // overrun error
#define SIO_LSR_PE 0x04 // parity error
#define SIO_LSR_FE 0x08 // framing error
#define SIO_LSR_BI 0x10 // break interrupt
#define SIO_LSR_THRE 0x20 // transmitter holding register empty
#define SIO_LSR_TEMT 0x40 // transmitter register empty
#define SIO_LSR_ERR 0x80 // any error condition
// The modem status register bits.
#define SIO_MSR_DCTS 0x01 // delta clear to send
#define SIO_MSR_DDSR 0x02 // delta data set ready
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
#define SIO_MSR_DDCD 0x08 // delta data carrier detect
#define SIO_MSR_CTS 0x10 // clear to send
#define SIO_MSR_DSR 0x20 // data set ready
#define SIO_MSR_RI 0x40 // ring indicator
#define SIO_MSR_DCD 0x80 // data carrier detect
// The line control register bits.
#define SIO_LCR_WLS0 0x01 // word length select bit 0
#define SIO_LCR_WLS1 0x02 // word length select bit 1
#define SIO_LCR_STB 0x04 // number of stop bits
#define SIO_LCR_PEN 0x08 // parity enable
#define SIO_LCR_EPS 0x10 // even parity select
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
// The FIFO control register
#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
//-----------------------------------------------------------------------------
static void
init_serial_channel(const channel_data_t* __ch_data)
{
cyg_uint8* base = __ch_data->base;
cyg_uint8 lcr;
// 8-1-no parity.
lcr = SIO_LCR_WLS0 | SIO_LCR_WLS1;
lcr |= SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
lcr &= ~SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
}
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
if ((lsr & SIO_LSR_DR) == 0)
return false;
HAL_READ_UINT8(base+CYG_DEV_SERIAL_RBR, *ch);
return true;
}
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
CYGARC_HAL_RESTORE_GP();
return ch;
}
void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
CYGARC_HAL_SAVE_GP();
do {
HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
} while ((lsr & SIO_LSR_THRE) == 0);
HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_THR, c);
// Hang around until the character has been safely sent.
do {
HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
} while ((lsr & SIO_LSR_THRE) == 0);
CYGARC_HAL_RESTORE_GP();
}
static const channel_data_t channels[2] = {
{ (cyg_uint8*)CYG_DEV_SERIAL_BASE_A, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_A},
{ (cyg_uint8*)CYG_DEV_SERIAL_BASE_B, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_B}
};
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
CYGARC_HAL_RESTORE_GP();
}
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
CYGARC_HAL_RESTORE_GP();
}
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 ier;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
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