interrupts.c

基于ecos的redboot

		/* don't print configuration secondary bridge errors */

		/* clear the interrupt condition */
		AND_WORD((volatile unsigned long *)SBISR_ADDR, 0x7f);
		CLEAR_SBRIDGE_STATUS();

		/* tell the config cleanup code about error */
		if (pci_config_cycle == 1) 
			pci_config_error = TRUE;
	}

	if (nmi_status & DMA_0_ERROR)
	{
		srcs_found++;
		error_print ("**** DMA Channel 0 Error ****\n",0,0,0,0);
		status = *(volatile unsigned long *)CSR0_ADDR;
		if (status & 0x001) error_print ("DMA Channel 0 PCI Parity Error\n",0,0,0,0);
		if (status & 0x004) error_print ("DMA Channel 0 PCI Target Abort\n",0,0,0,0);
		if (status & 0x008) error_print ("DMA Channel 0 PCI Master Abort\n",0,0,0,0);
		if (status & 0x020) error_print ("Internal PCI Master Abort\n",0,0,0,0);    
		/* clear the interrupt condition */
		AND_WORD((volatile unsigned long *)CSR0_ADDR, 0x2D);
	}

	if (nmi_status & DMA_1_ERROR)
	{
		srcs_found++;
		error_print ("**** DMA Channel 1 Error ****\n",0,0,0,0);
		status = *(volatile unsigned long *)CSR1_ADDR;
		if (status & 0x001) error_print ("DMA Channel 1 PCI Parity Error\n",0,0,0,0);
		if (status & 0x004) error_print ("DMA Channel 1 PCI Target Abort\n",0,0,0,0);
		if (status & 0x008) error_print ("DMA Channel 1 PCI Master Abort\n",0,0,0,0);
		if (status & 0x020) error_print ("Internal PCI Master Abort\n",0,0,0,0);  
	    
		/* clear the interrupt condition */
		AND_WORD((volatile unsigned long *)CSR1_ADDR, 0x2D);
	}

	if (nmi_status & DMA_2_ERROR)
	{
		srcs_found++;
		error_print ("**** DMA Channel 2 Error ****\n",0,0,0,0);
		status = *(volatile unsigned long *)CSR2_ADDR;
		if (status & 0x001) error_print ("DMA Channel 2 PCI Parity Error\n",0,0,0,0);
		if (status & 0x004) error_print ("DMA Channel 2 PCI Target Abort\n",0,0,0,0);
		if (status & 0x008) error_print ("DMA Channel 2 PCI Master Abort\n",0,0,0,0);
		if (status & 0x020) error_print ("Internal PCI Master Abort\n",0,0,0,0);  
		
		/* clear the interrupt condition */
		AND_WORD((volatile unsigned long *)CSR2_ADDR, 0x2D);
	}

	if (nmi_status & MU_ERROR)
	{	
		status = *(volatile unsigned long *)IISR_ADDR;
		if (status & 0x20)
		{
			srcs_found++;
			error_print ("Messaging Unit Outbound Free Queue Overflow\n",0,0,0,0);

			/* clear the interrupt condition; note that the clearing of the NMI doorbell
			is handled by the PCI comms code */
		}	AND_WORD((volatile unsigned long *)IISR_ADDR, 0x20);	
	}

	if (nmi_status & AAU_ERROR)
	{
		srcs_found++;
		error_print ("**** Application Accelerator Unit Error ****\n",0,0,0,0);
		status = *(volatile unsigned long *)ASR_ADDR;
		if (status & 0x020) error_print ("Internal PCI Master Abort\n",0,0,0,0);

		/* clear the interrupt condition */
		AND_WORD((volatile unsigned long *)ASR_ADDR, 0x20);
	}

	if (nmi_status & BIU_ERROR)
	{
		srcs_found++;
		error_print ("**** Bus Interface Unit Error ****\n",0,0,0,0);
		status = *(volatile unsigned long *)BIUISR_ADDR;
		if (status & 0x004) error_print ("Internal PCI Master Abort\n",0,0,0,0);

		/* clear the interrupt condition */
		AND_WORD((volatile unsigned long *)BIUISR_ADDR, 0x04);
	}

	return (srcs_found);

}


/**********************************************************************
* isr_connect - Disconnect a user Interrupt Service Routine
*
* NOT TO BE USED FOR SPCI INTERRUPTS! - use pci_isr_connect instead
*
*/
int isr_connect(int int_num, void (*handler)(int), int arg)
{
    switch (int_num)
    {

	case DMA0_INT_ID:
	    usr_dma0_isr = handler;
	    usr_dma0_arg = arg;
	    break;
	case DMA1_INT_ID:
	    usr_dma1_isr = handler;
	    usr_dma1_arg = arg;
	    break;
	case DMA2_INT_ID:
	    usr_dma2_isr = handler;
	    usr_dma2_arg = arg;
	    break;
	case PM_INT_ID:
		usr_pm_isr = handler;
		usr_pm_arg = arg;
		break;
	case AA_INT_ID:
		usr_aa_isr = handler;
		usr_aa_arg = arg;
		break;
	case I2C_INT_ID: 
		usr_i2c_isr = handler;
		usr_i2c_arg = arg;
		break;
	case MU_INT_ID:
		usr_mu_isr = handler;
		usr_mu_arg = arg;
		break;
	case PATU_INT_ID:
		usr_patu_isr = handler;
		usr_patu_arg = arg;
		break;
	case TIMER_INT_ID:
		usr_timer_isr = handler;
		usr_timer_arg = arg;
		break;
	case ENET_INT_ID:
		usr_enet_isr = handler;
		usr_enet_arg = arg;
		break;
	case UART1_INT_ID:
		usr_uart1_isr = handler;
		usr_uart1_arg = arg;
		break;
	case UART2_INT_ID:
		usr_uart2_isr = handler;
		usr_uart2_arg = arg;
		break;
	default:
		return (ERROR);
		break;
	}

	return (OK);
}

/**********************************************************************
* isr_disconnect - Disconnect a user Interrupt Service Routine
*
* NOT TO BE USED FOR SPCI INTERRUPTS! - use pci_isr_disconnect instead
*
*/
int isr_disconnect(int int_num)
{
    switch (int_num)
    {

	case DMA0_INT_ID:
	    usr_dma0_isr = NULL;
	    usr_dma0_arg = 0;
	    break;
	case DMA1_INT_ID:
	    usr_dma1_isr = NULL;
	    usr_dma1_arg = 0;
	    break;
	case DMA2_INT_ID:
	    usr_dma2_isr = NULL;
	    usr_dma2_arg = 0;
	    break;
	case PM_INT_ID:
		usr_pm_isr = NULL;
		usr_pm_arg = 0;
		break;
	case AA_INT_ID:
		usr_aa_isr = NULL;
		usr_aa_arg = 0;
		break;
	case I2C_INT_ID: 
		usr_i2c_isr = NULL;
		usr_i2c_arg = 0;
		break;
	case MU_INT_ID:
		usr_mu_isr = NULL;
		usr_mu_arg = 0;
		break;
	case PATU_INT_ID:
		usr_patu_isr = NULL;
		usr_patu_arg = 0;
		break;
	case TIMER_INT_ID:
		usr_timer_isr = NULL;
		usr_timer_arg = 0;
		break;
	case ENET_INT_ID:
		usr_enet_isr = NULL;
		usr_enet_arg = 0;
		break;
	case UART1_INT_ID:
		usr_uart1_isr = NULL;
		usr_uart1_arg = 0;
		break;
	case UART2_INT_ID:
		usr_uart2_isr = NULL;
		usr_uart2_arg = 0;
		break;
	default:
		return (ERROR);
		break;
	}

	/* i960 disabled interrupt here - should we? */

	return (OK);
}

/********************************************************************
* disable_external_interrupt - Mask an external interrupt 
*
*/
int disable_external_interrupt(int int_id)
{

unsigned char* ext_mask_reg = (unsigned char*) X3MASK_ADDR;
unsigned char  new_mask_value;

	/* make sure interrupt to enable is an external interrupt */
	if ((int_id < TIMER_INT_ID) || (int_id > SINTD_INT_ID))
		return (ERROR);

	new_mask_value = *ext_mask_reg; /* read current mask status */
	
	switch (int_id)
	{
	case TIMER_INT_ID:
		new_mask_value |= TIMER_INT;
		break;
	case ENET_INT_ID:
		new_mask_value |= ENET_INT;
		break;
	case UART1_INT_ID:
		new_mask_value |= UART1_INT;
		break;
	case UART2_INT_ID:
		new_mask_value |= UART2_INT;
		break;
	case SINTD_INT_ID:
		new_mask_value |= SINTD_INT;
		break;
	default:
		break; /* leave mask register as it was */
	}

	*ext_mask_reg = new_mask_value; /* set new mask value */

	return (OK);

}



/********************************************************************
* enable_external_interrupt - Unmask an external interrupt 
*
*/
int enable_external_interrupt(int int_id)
{

unsigned char* ext_mask_reg = (unsigned char*) X3MASK_ADDR;
unsigned char  new_mask_value;

	/* make sure interrupt to enable is an external interrupt */
	if ((int_id < TIMER_INT_ID) || (int_id > SINTD_INT_ID))
		return (ERROR);

	
	new_mask_value = *ext_mask_reg; /* read current mask status */
	
	switch (int_id)
	{
	case TIMER_INT_ID:
		new_mask_value &= ~(TIMER_INT);
		break;
	case ENET_INT_ID:
		new_mask_value &= ~(ENET_INT);
		break;
	case UART1_INT_ID:
		new_mask_value &= ~(UART1_INT);
		break;
	case UART2_INT_ID:
		new_mask_value &= ~(UART2_INT);
		break;
	case SINTD_INT_ID:
		new_mask_value &= ~(SINTD_INT);
		break;
	default:
		break; /* leave mask register as it was */
	}

	*ext_mask_reg = new_mask_value; /* set new mask value */

	return (OK);
}


void error_print (
		char *fmt,
		int arg0,
		int arg1,
		int arg2,
		int arg3
		)
{
	/* Wait until host configures the boards to start printing NMI errors */
	UINT32* atu_reg = (UINT32*)PIABAR_ADDR;
	if ((*atu_reg & 0xfffffff0) == 0)
		return;
	if (nmi_verbose) printf (fmt, arg0, arg1, arg2, arg3);
		return;
}

extern void __diag_IRQ(void);
extern void __diag_FIQ(void);

void config_ints()
{
int xint, x;
	
	unsigned int* pirsr_ptr = (unsigned int*)PIRSR_ADDR;
	*pirsr_ptr = 0xf; /* this is an errata in the original Yavapai manual.
					     The interrupt steering bits are reversed, so a '1'
						 routes XINT interrupts to FIQ
						*/

	/* install diag IRQ handlers */
	((volatile unsigned *)0x20)[6] = (unsigned)__diag_IRQ;
	((volatile unsigned *)0x20)[7] = (unsigned)__diag_FIQ;
	_flushICache();	

	/* make sure interrupts are enabled in CSPR */

	_cspr_enable_irq_int(); 

	_cspr_enable_fiq_int(); 

	/* initialize the PCI interrupt table */
	for (xint = 0; xint < NUM_PCI_XINTS; xint++)
	{
		for (x = 0; x < MAX_PCI_HANDLERS; x++) 
		{
			pci_int_handlers[xint][x].handler	= NULL;
			pci_int_handlers[xint][x].arg		= (int)NULL;
			pci_int_handlers[xint][x].bus		= (int)NULL;
			pci_int_handlers[xint][x].device	= (int)NULL;
		}
	}


}