hal_sa11x0.h

基于ecos的redboot

#define SA11X0_WAKEUP_ENABLE(x)                  ((x) & 0x8FFFFFFF)

/*
 * SA-1100 Power Manager Sleep Status Bit Field Definitions
 */
#define SA11X0_SOFTWARE_SLEEP_STATUS             0x00000001
#define SA11X0_BATTERY_FAULT_STATUS              0x00000002
#define SA11X0_VDD_FAULT_STATUS                  0x00000004
#define SA11X0_DRAM_CONTROL_HOLD                 0x00000008
#define SA11X0_PERIPHERAL_CONTROL_HOLD           0x00000010

/*
 * SA-1100 Power Manager Oscillator Status Register Bit Field Definitions
 */
#define SA11X0_OSCILLATOR_STATUS                 0x00000001

/*
 * SA-1110 GPCLK Register Definitions
 */
#define SA1110_GPCLK_CONTROL_0                   SA11X0_REGISTER(0x00020060)
#define SA1110_GPCLK_CONTROL_1                   SA11X0_REGISTER(0x0002006C)
#define SA1110_GPCLK_CONTROL_2                   SA11X0_REGISTER(0x00020070)

/* GPCLK Control Register 0 */
#define SA1110_GPCLK_SUS_GPCLK   0
#define SA1110_GPCLK_SUS_UART    1
#define SA1110_GPCLK_SCE         2
#define SA1110_GPCLK_SCD_IN      0
#define SA1110_GPCLK_SCD_OUT     4

/*
 * SA11X0 Peripheral Port Controller Register Definitions
 */
#define SA11X0_PPC_PIN_DIRECTION                 SA11X0_REGISTER(0x10060000)
#define SA11X0_PPC_PIN_STATE                     SA11X0_REGISTER(0x10060004)
#define SA11X0_PPC_PIN_ASSIGNMENT                SA11X0_REGISTER(0x10060008)
#define SA11X0_PPC_PIN_SLEEP_MODE_DIR            SA11X0_REGISTER(0x1006000C)
#define SA11X0_PPC_PIN_FLAG                      SA11X0_REGISTER(0x10060010)

/*
 * SA11X0 PPC Bit Field Definitions
 */
#define SA11X0_PPC_LCD_PIN_0_DIR_INPUT           0x00000000
#define SA11X0_PPC_LCD_PIN_0_DIR_OUTPUT          0x00000001
#define SA11X0_PPC_LCD_PIN_0_DIR_MASK            0x00000001
#define SA11X0_PPC_LCD_PIN_1_DIR_INPUT           0x00000000
#define SA11X0_PPC_LCD_PIN_1_DIR_OUTPUT          0x00000002
#define SA11X0_PPC_LCD_PIN_1_DIR_MASK            0x00000002
#define SA11X0_PPC_LCD_PIN_2_DIR_INPUT           0x00000000
#define SA11X0_PPC_LCD_PIN_2_DIR_OUTPUT          0x00000004
#define SA11X0_PPC_LCD_PIN_2_DIR_MASK            0x00000004
#define SA11X0_PPC_LCD_PIN_3_DIR_INPUT           0x00000000
#define SA11X0_PPC_LCD_PIN_3_DIR_OUTPUT          0x00000008
#define SA11X0_PPC_LCD_PIN_3_DIR_MASK            0x00000008
#define SA11X0_PPC_LCD_PIN_4_DIR_INPUT           0x00000000
#define SA11X0_PPC_LCD_PIN_4_DIR_OUTPUT          0x00000010
#define SA11X0_PPC_LCD_PIN_4_DIR_MASK            0x00000010
#define SA11X0_PPC_LCD_PIN_5_DIR_INPUT           0x00000000
#define SA11X0_PPC_LCD_PIN_5_DIR_OUTPUT          0x00000020
#define SA11X0_PPC_LCD_PIN_5_DIR_MASK            0x00000020
#define SA11X0_PPC_LCD_PIN_6_DIR_INPUT           0x00000000
#define SA11X0_PPC_LCD_PIN_6_DIR_OUTPUT          0x00000040
#define SA11X0_PPC_LCD_PIN_6_DIR_MASK            0x00000040
#define SA11X0_PPC_LCD_PIN_7_DIR_INPUT           0x00000000
#define SA11X0_PPC_LCD_PIN_7_DIR_OUTPUT          0x00000080
#define SA11X0_PPC_LCD_PIN_7_DIR_MASK            0x00000080
#define SA11X0_PPC_LCD_PIXCLK_DIR_INPUT          0x00000000
#define SA11X0_PPC_LCD_PIXCLK_DIR_OUTPUT         0x00000100
#define SA11X0_PPC_LCD_PIXCLK_DIR_MASK           0x00000100
#define SA11X0_PPC_LCD_LINECLK_DIR_INPUT         0x00000000
#define SA11X0_PPC_LCD_LINECLK_DIR_OUTPUT        0x00000200
#define SA11X0_PPC_LCD_LINECLK_DIR_MASK          0x00000200
#define SA11X0_PPC_LCD_FRAMECLK_DIR_INPUT        0x00000000
#define SA11X0_PPC_LCD_FRAMECLK_DIR_OUTPUT       0x00000400
#define SA11X0_PPC_LCD_FRAMECLK_DIR_MASK         0x00000400
#define SA11X0_PPC_LCD_AC_BIAS_DIR_INPUT         0x00000000
#define SA11X0_PPC_LCD_AC_BIAS_DIR_OUTPUT        0x00000800
#define SA11X0_PPC_LCD_AC_BIAS_DIR_MASK          0x00000800
#define SA11X0_PPC_SERIAL_PORT_1_TX_DIR_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_1_TX_DIR_OUTPUT   0x00001000
#define SA11X0_PPC_SERIAL_PORT_1_TX_DIR_MASK     0x00001000
#define SA11X0_PPC_SERIAL_PORT_1_RX_DIR_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_1_RX_DIR_OUTPUT   0x00002000
#define SA11X0_PPC_SERIAL_PORT_1_RX_DIR_MASK     0x00002000
#define SA11X0_PPC_SERIAL_PORT_2_TX_DIR_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_2_TX_DIR_OUTPUT   0x00004000
#define SA11X0_PPC_SERIAL_PORT_2_TX_DIR_MASK     0x00004000
#define SA11X0_PPC_SERIAL_PORT_2_RX_DIR_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_2_RX_DIR_OUTPUT   0x00008000
#define SA11X0_PPC_SERIAL_PORT_2_RX_DIR_MASK     0x00008000
#define SA11X0_PPC_SERIAL_PORT_3_TX_DIR_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_3_TX_DIR_OUTPUT   0x00010000
#define SA11X0_PPC_SERIAL_PORT_3_TX_DIR_MASK     0x00010000
#define SA11X0_PPC_SERIAL_PORT_3_RX_DIR_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_3_RX_DIR_OUTPUT   0x00020000
#define SA11X0_PPC_SERIAL_PORT_3_RX_DIR_MASK     0x00020000
#define SA11X0_PPC_SERIAL_PORT_4_TX_DIR_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_4_TX_DIR_OUTPUT   0x00040000
#define SA11X0_PPC_SERIAL_PORT_4_TX_DIR_MASK     0x00040000
#define SA11X0_PPC_SERIAL_PORT_4_RX_DIR_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_4_RX_DIR_OUTPUT   0x00080000
#define SA11X0_PPC_SERIAL_PORT_4_RX_DIR_MASK     0x00080000
#define SA11X0_PPC_SERIAL_PORT_4_SERCLK_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_4_SERCLK_OUTPUT   0x00100000
#define SA11X0_PPC_SERIAL_PORT_4_SERCLK_MASK     0x00100000
#define SA11X0_PPC_SERIAL_PORT_4_SERFRM_INPUT    0x00000000
#define SA11X0_PPC_SERIAL_PORT_4_SERFRM_OUTPUT   0x00200000
#define SA11X0_PPC_SERIAL_PORT_4_SERFRM_MASK     0x00200000

#define SA11X0_PPC_UART_PIN_NOT_REASSIGNED       0x00000000
#define SA11X0_PPC_UART_PIN_REASSIGNED           0x00001000
#define SA11X0_PPC_UART_PIN_REASSIGNMENT_MASK    0x00001000
#define SA11X0_PPC_SSP_PIN_NOT_REASSIGNED        0x00000000
#define SA11X0_PPC_SSP_PIN_REASSIGNED            0x00040000
#define SA11X0_PPC_SSP_PIN_REASSIGNMENT_MASK     0x00040000

/*
 * SA-1100 MCP Registers
 */
#define SA11X0_MCP_CONTROL_0                     SA11X0_REGISTER(0x00060000)
#define SA11X0_MCP_DATA_0                        SA11X0_REGISTER(0x00060008)
#define SA11X0_MCP_DATA_1                        SA11X0_REGISTER(0x0006000C)
#define SA11X0_MCP_DATA_2                        SA11X0_REGISTER(0x00060010)
#define SA11X0_MCP_STATUS                        SA11X0_REGISTER(0x00060018)
#define SA11X0_MCP_CONTROL_1                     SA11X0_REGISTER(0x00060030)

/*
 * SA-1100 Memory Configuration Registers
 */
#define SA11X0_DRAM_CONFIGURATION                SA11X0_REGISTER(0x20000000)
#define SA11X0_DRAM0_CAS_0                       SA11X0_REGISTER(0x20000004)
#define SA11X0_DRAM0_CAS_1                       SA11X0_REGISTER(0x20000008)
#define SA11X0_DRAM0_CAS_2                       SA11X0_REGISTER(0x2000000C)
#define SA11X0_STATIC_CONTROL_0                  SA11X0_REGISTER(0x20000010)
#define SA11X0_STATIC_CONTROL_1                  SA11X0_REGISTER(0x20000014)
#define SA11X0_EXP_BUS_CONFIGURATION             SA11X0_REGISTER(0x20000018)
#define SA11X0_REFRESH_CONFIGURATION             SA11X0_REGISTER(0x2000001C)
#define SA11X0_DRAM2_CAS_0                       SA11X0_REGISTER(0x20000020)
#define SA11X0_DRAM2_CAS_1                       SA11X0_REGISTER(0x20000024)
#define SA11X0_DRAM2_CAS_2                       SA11X0_REGISTER(0x20000028)
#define SA11X0_STATIC_CONTROL_2                  SA11X0_REGISTER(0x2000002C)
#define SA11X0_SMROM_CONFIGURATION               SA11X0_REGISTER(0x20000030)

/*
 * SA-1100 DRAM Configuration Bit Field Definitions
 */
#define SA11X0_DRAM_BANK_0_DISABLED              0x00000000
#define SA11X0_DRAM_BANK_0_ENABLED               0x00000001
#define SA11X0_DRAM_BANK_0_ENABLE_MASK           0x00000001
#define SA11X0_DRAM_BANK_1_DISABLED              0x00000000
#define SA11X0_DRAM_BANK_1_ENABLED               0x00000002
#define SA11X0_DRAM_BANK_1_ENABLE_MASK           0x00000002
#define SA11X0_DRAM_BANK_2_DISABLED              0x00000000
#define SA11X0_DRAM_BANK_2_ENABLED               0x00000004
#define SA11X0_DRAM_BANK_2_ENABLE_MASK           0x00000004
#define SA11X0_DRAM_BANK_3_DISABLED              0x00000000
#define SA11X0_DRAM_BANK_3_ENABLED               0x00000008
#define SA11X0_DRAM_BANK_3_ENABLE_MASK           0x00000008
#define SA11X0_DRAM_ROW_ADDRESS_BITS_9           0x00000000
#define SA11X0_DRAM_ROW_ADDRESS_BITS_10          0x00000010
#define SA11X0_DRAM_ROW_ADDRESS_BITS_11          0x00000020
#define SA11X0_DRAM_ROW_ADDRESS_BITS_12          0x00000030
#define SA11X0_DRAM_ROW_ADDRESS_BITS_MASK        0x00000030
#define SA11X0_DRAM_CLOCK_CPU_CLOCK              0x00000000
#define SA11X0_DRAM_CLOCK_CPU_CLOCK_DIV_2        0x00000040
#define SA11X0_DRAM_CLOCK_CPU_CLOCK_MASK         0x00000040
#define SA11X0_DRAM_RAS_PRECHARGE(x)             (((x) & 0xF) << 7)
#define SA11X0_DRAM_CAS_BEFORE_RAS(x)            (((x) & 0xF) << 11)
#define SA11X0_DATA_INPUT_LATCH_WITH_CAS         0x00000000
#define SA11X0_DATA_INPUT_LATCH_CAS_PLUS_ONE     0x00008000
#define SA11X0_DATA_INPUT_LATCH_CAS_PLUS_TWO     0x00010000
#define SA11X0_DATA_INPUT_LATCH_CAS_PLUS_THREE   0x00018000
#define SA11X0_DRAM_REFRESH_INTERVAL(x)          (((x) & 0x7FFF) << 17)

/*
 * SA-1100 Static Memory Control Register Bit Field Definitions
 */
#define SA11X0_STATIC_ROM_TYPE_FLASH             0x00000000
#define SA11X0_STATIC_ROM_TYPE_SRAM              0x00000001
#define SA11X0_STATIC_ROM_TYPE_BURST_OF_4_ROM    0x00000002
#define SA11X0_STATIC_ROM_TYPE_BURST_OF_8_ROM    0x00000003
#define SA11X0_STATIC_ROM_TYPE_MASK              0x00000003
#define SA11X0_STATIC_ROM_BUS_WIDTH_32_BITS      0x00000000
#define SA11X0_STATIC_ROM_BUS_WIDTH_16_BITS      0x00000004
#define SA11X0_STATIC_ROM_BUS_WIDTH_MASK         0x00000004
#define SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(x)  (((x) & 0x1F) << 3)
#define SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(x)   (((x) & 0x1F) << 8)
#define SA11X0_STATIC_ROM_RECOVERY(x)            (((x) & 0x7) << 13)

#define SA11X0_STATIC_ROM_BANK_0(x)              (((x) & 0xFFFF) <<  0)
#define SA11X0_STATIC_ROM_BANK_1(x)              (((x) & 0xFFFF) << 16)
#define SA11X0_STATIC_ROM_BANK_2(x)              (((x) & 0xFFFF) <<  0)
#define SA11X0_STATIC_ROM_BANK_3(x)              (((x) & 0xFFFF) << 16)

/*
 * SA-1100 GPIO Register Definitions
 */
#define SA11X0_GPIO_PIN_0                        (1 << 0)
#define SA11X0_GPIO_PIN_1                        (1 << 1)
#define SA11X0_GPIO_PIN_2                        (1 << 2)
#define SA11X0_GPIO_PIN_3                        (1 << 3)
#define SA11X0_GPIO_PIN_4                        (1 << 4)
#define SA11X0_GPIO_PIN_5                        (1 << 5)
#define SA11X0_GPIO_PIN_6                        (1 << 6)
#define SA11X0_GPIO_PIN_7                        (1 << 7)
#define SA11X0_GPIO_PIN_8                        (1 << 8)
#define SA11X0_GPIO_PIN_9                        (1 << 9)
#define SA11X0_GPIO_PIN_10                       (1 << 10)
#define SA11X0_GPIO_PIN_11                       (1 << 11)
#define SA11X0_GPIO_PIN_12                       (1 << 12)
#define SA11X0_GPIO_PIN_13                       (1 << 13)
#define SA11X0_GPIO_PIN_14                       (1 << 14)
#define SA11X0_GPIO_PIN_15                       (1 << 15)
#define SA11X0_GPIO_PIN_16                       (1 << 16)
#define SA11X0_GPIO_PIN_17                       (1 << 17)
#define SA11X0_GPIO_PIN_18                       (1 << 18)
#define SA11X0_GPIO_PIN_19                       (1 << 19)
#define SA11X0_GPIO_PIN_20                       (1 << 20)
#define SA11X0_GPIO_PIN_21                       (1 << 21)
#define SA11X0_GPIO_PIN_22                       (1 << 22)
#define SA11X0_GPIO_PIN_23                       (1 << 23)
#define SA11X0_GPIO_PIN_24                       (1 << 24)
#define SA11X0_GPIO_PIN_25                       (1 << 25)
#define SA11X0_GPIO_PIN_26                       (1 << 26)
#define SA11X0_GPIO_PIN_27                       (1 << 27)

#define SA11X0_GPIO_PIN_LEVEL                    SA11X0_REGISTER(0x10040000)
#define SA11X0_GPIO_PIN_DIRECTION                SA11X0_REGISTER(0x10040004)
#define SA11X0_GPIO_PIN_OUTPUT_SET               SA11X0_REGISTER(0x10040008)
#define SA11X0_GPIO_PIN_OUTPUT_CLEAR             SA11X0_REGISTER(0x1004000C)
#define SA11X0_GPIO_RISING_EDGE_DETECT           SA11X0_REGISTER(0x10040010)
#define SA11X0_GPIO_FALLING_EDGE_DETECT          SA11X0_REGISTER(0x10040014)
#define SA11X0_GPIO_EDGE_DETECT_STATUS           SA11X0_REGISTER(0x10040018)
#define SA11X0_GPIO_ALTERNATE_FUNCTION           SA11X0_REGISTER(0x1004001C)

#endif /* __HAL_SA11X0_H__ */