hal_sa11x0.h

基于ecos的redboot

#define SA11X0_IRQ_CHANNEL_4_SERVICE_REQUEST     24
#define SA11X0_IRQ_CHANNEL_5_SERVICE_REQUEST     25
#define SA11X0_IRQ_OS_TIMER_MATCH_REG_0          26
#define SA11X0_IRQ_OS_TIMER_MATCH_REG_1          27
#define SA11X0_IRQ_OS_TIMER_MATCH_REG_2          28
#define SA11X0_IRQ_OS_TIMER_MATCH_REG_3          29
#define SA11X0_IRQ_ONE_HZ_CLOCK_TIC              30
#define SA11X0_IRQ_RTC_EQUALS_ALARM              31
                                                 
#define SA11X0_IRQ_MAX                           31
#define NUM_SA11X0_INTERRUPTS                    SA11X0_IRQ_MAX - SA11X0_IRQ_MIN + 1
#define SA11X0_IRQ_INTSRC_MASK(irq_nr)           (1 << (irq_nr))

/*
 * SA11X0 UART 1 Registers
 */
#define SA11X0_UART1_BASE                       SA11X0_REGISTER(0x10000)
#define SA11X0_UART1_CONTROL0                   SA11X0_REGISTER(0x10000)
#define SA11X0_UART1_CONTROL1                   SA11X0_REGISTER(0x10004)
#define SA11X0_UART1_CONTROL2                   SA11X0_REGISTER(0x10008)
#define SA11X0_UART1_CONTROL3                   SA11X0_REGISTER(0x1000C)
#define SA11X0_UART1_DATA                       SA11X0_REGISTER(0x10014)
#define SA11X0_UART1_STATUS0                    SA11X0_REGISTER(0x1001C)
#define SA11X0_UART1_STATUS1                    SA11X0_REGISTER(0x10020)

/*
 * SA11X0 UART 3 Registers
 */
#define SA11X0_UART3_BASE                       SA11X0_REGISTER(0x50000)
#define SA11X0_UART3_CONTROL0                   SA11X0_REGISTER(0x50000)
#define SA11X0_UART3_CONTROL1                   SA11X0_REGISTER(0x50004)
#define SA11X0_UART3_CONTROL2                   SA11X0_REGISTER(0x50008)
#define SA11X0_UART3_CONTROL3                   SA11X0_REGISTER(0x5000C)
#define SA11X0_UART3_DATA                       SA11X0_REGISTER(0x50014)
#define SA11X0_UART3_STATUS0                    SA11X0_REGISTER(0x5001C)
#define SA11X0_UART3_STATUS1                    SA11X0_REGISTER(0x50020)

/*
 * SA11X0 UART Control Register 0 Bit Fields.
 */
#define SA11X0_UART_PARITY_DISABLED              0x00
#define SA11X0_UART_PARITY_ENABLED               0x01
#define SA11X0_UART_PARITY_ENABLE_MASK           0x01
#define SA11X0_UART_PARITY_ODD                   0x00
#define SA11X0_UART_PARITY_EVEN                  0x02
#define SA11X0_UART_PARITY_MODE_MASK             0x02
#define SA11X0_UART_STOP_BITS_1                  0x00
#define SA11X0_UART_STOP_BITS_2                  0x04
#define SA11X0_UART_STOP_BITS_MASK               0x04
#define SA11X0_UART_DATA_BITS_7                  0x00
#define SA11X0_UART_DATA_BITS_8                  0x08
#define SA11X0_UART_DATA_BITS_MASK               0x08
#define SA11X0_UART_SAMPLE_CLOCK_DISABLED        0x00
#define SA11X0_UART_SAMPLE_CLOCK_ENABLED         0x10
#define SA11X0_UART_SAMPLE_CLOCK_ENABLE_MASK     0x10
#define SA11X0_UART_RX_RISING_EDGE_SELECT        0x00
#define SA11X0_UART_RX_FALLING_EDGE_SELECT       0x20
#define SA11X0_UART_RX_EDGE_SELECT_MASK          0x20
#define SA11X0_UART_TX_RISING_EDGE_SELECT        0x00
#define SA11X0_UART_TX_FALLING_EDGE_SELECT       0x40
#define SA11X0_UART_TX_EDGE_SELECT_MASK          0x20

/*
 * SA-1100 UART Baud Control Register bit masks
 */
#define SA11X0_UART_H_BAUD_RATE_DIVISOR_MASK     0x0000000F
#define SA11X0_UART_L_BAUD_RATE_DIVISOR_MASK     0x000000FF
#define SA11X0_UART_BAUD_RATE_DIVISOR(x)         ((3686400/(16*(x)))-1)

/*
 * SA-1100 UART Control Register 3 Bit Fields.
 */
#define SA11X0_UART_RX_DISABLED                  0x00
#define SA11X0_UART_RX_ENABLED                   0x01
#define SA11X0_UART_RX_ENABLE_MASK               0x01
#define SA11X0_UART_TX_DISABLED                  0x00
#define SA11X0_UART_TX_ENABLED                   0x02
#define SA11X0_UART_TX_ENABLE_MASK               0x02
#define SA11X0_UART_BREAK_DISABLED               0x00
#define SA11X0_UART_BREAK_ENABLED                0x04
#define SA11X0_UART_BREAK_MASK                   0x04
#define SA11X0_UART_RX_FIFO_INT_DISABLED         0x00
#define SA11X0_UART_RX_FIFO_INT_ENABLED          0x08
#define SA11X0_UART_RX_FIFO_INT_ENABLE_MASK      0x08
#define SA11X0_UART_TX_FIFO_INT_DISABLED         0x00
#define SA11X0_UART_TX_FIFO_INT_ENABLED          0x10
#define SA11X0_UART_TX_FIFO_INT_ENABLE_MASK      0x10
#define SA11X0_UART_NORMAL_OPERATION             0x00
#define SA11X0_UART_LOOPBACK_MODE                0x20

/*
 * SA-1100 UART Data Register bit masks
 */
#define SA11X0_UART_DATA_MASK                    0x000000FF

/*
 * SA-1100 UART Status Register 0 Bit Fields.
 */
#define SA11X0_UART_TX_SERVICE_REQUEST           0x01
#define SA11X0_UART_RX_SERVICE_REQUEST           0x02
#define SA11X0_UART_RX_IDLE                      0x04
#define SA11X0_UART_RX_BEGIN_OF_BREAK            0x08
#define SA11X0_UART_RX_END_OF_BREAK              0x10
#define SA11X0_UART_ERROR_IN_FIFO                0x20

/*
 * SA-1100 UART Status Register 1 Bit Fields.
 */
#define SA11X0_UART_TX_BUSY                      0x01
#define SA11X0_UART_RX_FIFO_NOT_EMPTY            0x02
#define SA11X0_UART_TX_FIFO_NOT_FULL             0x04
#define SA11X0_UART_PARITY_ERROR                 0x08
#define SA11X0_UART_FRAMING_ERROR                0x10
#define SA11X0_UART_RX_FIFO_OVERRUN              0x20

#define UART_BASE_0                              SA11X0_UART_CONTROL_0
#define UART_BASE_1                              SA11X0_UART_1_CONTROL_0

/*
 * SA11X0 IRQ Controller Register Definitions.
 */
#define SA11X0_ICIP                              SA11X0_REGISTER(0x10050000)
#define SA11X0_ICMR                              SA11X0_REGISTER(0x10050004)
#define SA11X0_ICLR                              SA11X0_REGISTER(0x10050008)
#define SA11X0_ICCR                              SA11X0_REGISTER(0x1005000C)
#define SA11X0_ICFP                              SA11X0_REGISTER(0x10050010)
#define SA11X0_ICPR                              SA11X0_REGISTER(0x10050020)

/*
 * SA11X0 IRQ Controller Control Register Bit Fields.
 */
#define SA11X0_ICCR_DISABLE_IDLE_MASK_ALL        0x0
#define SA11X0_ICCR_DISABLE_IDLE_MASK_ENABLED    0x1

/*
 * SA11X0 Timer/counter registers
 */
#define SA11X0_OSMR0                             SA11X0_REGISTER(0x10000000)
#define SA11X0_OSMR1                             SA11X0_REGISTER(0x10000004)
#define SA11X0_OSMR2                             SA11X0_REGISTER(0x10000008)
#define SA11X0_OSMR3                             SA11X0_REGISTER(0x1000000C)
#define SA11X0_OSCR                              SA11X0_REGISTER(0x10000010)
#define SA11X0_OSSR                              SA11X0_REGISTER(0x10000014)
#define SA11X0_OWER                              SA11X0_REGISTER(0x10000018)
#define SA11X0_OIER                              SA11X0_REGISTER(0x1000001C)
#define SA11X0_RCNR                              SA11X0_REGISTER(0x10010004)
#define SA11X0_RTTR                              SA11X0_REGISTER(0x10010008)
#define SA11X0_RTSR                              SA11X0_REGISTER(0x10010010)

// Timer status register
#define SA11X0_OSSR_TIMER0  (1<<0)   // Timer match register #0
#define SA11X0_OSSR_TIMER1  (1<<1)
#define SA11X0_OSSR_TIMER2  (1<<2)
#define SA11X0_OSSR_TIMER3  (1<<3)

// Timer interrupt enable register
#define SA11X0_OIER_TIMER0  (1<<0)
#define SA11X0_OIER_TIMER1  (1<<1)
#define SA11X0_OIER_TIMER2  (1<<2)
#define SA11X0_OIER_TIMER3  (1<<3)

// OS Timer Watchdog Match Enable Register
#define SA11X0_OWER_ENABLE  (1<<0) // write-once!

/*
 * SA-1100 Reset Controller Register Definition
 */
#define SA11X0_RESET_SOFTWARE_RESET              SA11X0_REGISTER(0x10030000)
#define SA11X0_RESET_STATUS                      SA11X0_REGISTER(0x10030004)
#define SA11X0_TUCR                              SA11X0_REGISTER(0x10030008)

#define SA11X0_TUCR_EXTERNAL_MEMORY_MASTER       (1<<10)
#define SA11X0_TUCR_RESERVED_BITS                0x1FFFF9FF

/*
 * SA-1100 Reset Controller Bit Field Definitions
 */
#define SA11X0_INVOKE_SOFTWARE_RESET             0x1

#define SA11X0_HARDWARE_RESET                    0x1
#define SA11X0_SOFTWARE_RESET                    0x2
#define SA11X0_WATCHDOG_RESET                    0x4
#define SA11X0_SLEEP_MODE_RESET                  0x8

/*
 * SA-1100 Power Manager Registers
 */
#define SA11X0_PWR_MGR_CONTROL                   SA11X0_REGISTER(0x10020000)
#define SA11X0_PWR_MGR_SLEEP_STATUS              SA11X0_REGISTER(0x10020004)
#define SA11X0_PWR_MGR_SCRATCHPAD                SA11X0_REGISTER(0x10020008)
#define SA11X0_PWR_MGR_WAKEUP_ENABLE             SA11X0_REGISTER(0x1002000C)
#define SA11X0_PWR_MGR_GENERAL_CONFIG            SA11X0_REGISTER(0x10020010)
#define SA11X0_PWR_MGR_PLL_CONFIG                SA11X0_REGISTER(0x10020014)
#define SA11X0_PWR_MGR_GPIO_SLEEP_STATE          SA11X0_REGISTER(0x10020018)
#define SA11X0_PWR_MGR_OSC_STATUS                SA11X0_REGISTER(0x1002001C)

/*
 * SA-1100 Control Register Bit Field Definitions
 */
#define SA11X0_NO_FORCE_SLEEP_MODE               0x00000000
#define SA11X0_FORCE_SLEEP_MODE                  0x00000001
#define SA11X0_SLEEP_MODE_MASK                   0x00000001

/*
 * SA-1100 Power Management Configuration Register Bit Field Definitions
 */
#define SA11X0_NO_STOP_OSC_DURING_SLEEP          0x00000000
#define SA11X0_STOP_OSC_DURING_SLEEP             0x00000001
#define SA11X0_OSC_DURING_SLEEP_MASK             0x00000001
#define SA11X0_DRIVE_PCMCIA_DURING_SLEEP         0x00000000
#define SA11X0_FLOAT_PCMCIA_DURING_SLEEP         0x00000002
#define SA11X0_PCMCIA_DURING_SLEEP_MASK          0x00000002
#define SA11X0_DRIVE_CHIPSEL_DURING_SLEEP        0x00000000
#define SA11X0_FLOAT_CHIPSEL_DURING_SLEEP        0x00000004
#define SA11X0_CHIPSEL_DURING_SLEEP_MASK         0x00000004
#define SA11X0_WAIT_OSC_STABLE                   0x00000000
#define SA11X0_FORCE_OSC_ENABLE_ON               0x00000008
#define SA11X0_OSC_STABLE_MASK                   0x00000008

/*
 * SA-1100 PLL Configuration Register Bit Field Definitions
 */
#define SA11X0_CLOCK_SPEED_59_0_MHz              0x00000000
#define SA11X0_CLOCK_SPEED_73_7_MHz              0x00000001
#define SA11X0_CLOCK_SPEED_88_5_MHz              0x00000002
#define SA11X0_CLOCK_SPEED_103_2_MHz             0x00000003
#define SA11X0_CLOCK_SPEED_118_0_MHz             0x00000004
#define SA11X0_CLOCK_SPEED_132_7_MHz             0x00000005
#define SA11X0_CLOCK_SPEED_147_5_MHz             0x00000006
#define SA11X0_CLOCK_SPEED_162_2_MHz             0x00000007
#define SA11X0_CLOCK_SPEED_176_9_MHz             0x00000008
#define SA11X0_CLOCK_SPEED_191_7_MHz             0x00000009
#define SA11X0_CLOCK_SPEED_206_4_MHz             0x0000000A
#define SA11X0_CLOCK_SPEED_221_2_MHz             0x0000000B

/*
 * SA-1100 Power Manager Wakeup Register Bit Field Definitions
 */