hal_sa11x0.h

基于ecos的redboot

//==========================================================================
//
//      hal_sa11x0.h
//
//      HAL misc board support definitions for StrongARM SA11x0
//
//==========================================================================
//####COPYRIGHTBEGIN####
//
// -------------------------------------------
// The contents of this file are subject to the Red Hat eCos Public License
// Version 1.1 (the "License"); you may not use this file except in
// compliance with the License.  You may obtain a copy of the License at
// http://www.redhat.com/
//
// Software distributed under the License is distributed on an "AS IS"
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the
// License for the specific language governing rights and limitations under
// the License. 
//
// The Original Code is eCos - Embedded Configurable Operating System,
// released September 30, 1998.
//
// The Initial Developer of the Original Code is Red Hat.
// Portions created by Red Hat are
// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
// All Rights Reserved.
// -------------------------------------------
//
//####COPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    gthomas
// Contributors: gthomas, dmoseley
// Date:         2000-04-04
// Purpose:      Platform register definitions
// Description:  
//
//####DESCRIPTIONEND####
//
//========================================================================*/

#ifndef __HAL_SA11X0_H__
#define __HAL_SA11X0_H__ 1

#ifdef __ASSEMBLER__

#define REG8_VAL(a)  (a)
#define REG16_VAL(a) (a)
#define REG32_VAL(a) (a)

#define REG8_PTR(a)  (a)
#define REG16_PTR(a) (a)
#define REG32_PTR(a) (a)

#else /* __ASSEMBLER__ */

#define REG8_VAL(a)  ((unsigned char)(a))
#define REG16_VAL(a) ((unsigned short)(a))
#define REG32_VAL(a) ((unsigned int)(a))

#define REG8_PTR(a)  ((volatile unsigned char *)(a))
#define REG16_PTR(a) ((volatile unsigned long *)(a))
#define REG32_PTR(a) ((volatile unsigned long *)(a))

#endif /* __ASSEMBLER__ */

/*
 * SA11X0 Default Memory Layout Definitions
 */
#define SA11X0_ROM_BANK0_BASE                    (0)
#define SA11X0_ROM_BANK1_BASE                    (SA11X0_ROM_BANK0_BASE + SZ_128M)
#define SA11X0_ROM_BANK2_BASE                    (SA11X0_ROM_BANK1_BASE + SZ_128M)
#define SA11X0_ROM_BANK3_BASE                    (SA11X0_ROM_BANK2_BASE + SZ_128M)

#define SA11X0_RAM_BANK0_BASE                    (0xC0000000)
#define SA11X0_RAM_BANK1_BASE                    (SA11X0_RAM_BANK0_BASE + SZ_128M)
#define SA11X0_RAM_BANK2_BASE                    (SA11X0_RAM_BANK1_BASE + SZ_128M)
#define SA11X0_RAM_BANK3_BASE                    (SA11X0_RAM_BANK2_BASE + SZ_128M)

#define SA11X0_ZEROS_BANK_BASE                   (SA11X0_RAM_BANK3_BASE + SZ_128M)

/*
 * SA11X0 Register Definitions
 */
#define SA11X0_REGISTER_BASE                     0x80000000
#define SA11X0_REGISTER(x)                       REG32_PTR(SA11X0_REGISTER_BASE + (x))

/*
 * SA-1100 Cache and MMU Definitions
 */
#define SA11X0_ICACHE_SIZE                       0x4000  // 16K
#define SA11X0_DCACHE_SIZE                       0x2000  // 8K
#define SA11X0_ICACHE_LINESIZE_BYTES             32
#define SA11X0_DCACHE_LINESIZE_BYTES             32
#define SA11X0_ICACHE_LINESIZE_WORDS             8
#define SA11X0_DCACHE_LINESIZE_WORDS             8
#define SA11X0_ICACHE_WAYS                       32
#define SA11X0_DCACHE_WAYS                       32
#define SA11X0_ICACHE_LINE_BASE(p)               REG32_PTR((unsigned long)(p) & \
                                                           ~(SA11X0_ICACHE_LINESIZE_BYTES - 1))
#define SA11X0_DCACHE_LINE_BASE(p)               REG32_PTR((unsigned long)(p) & \
                                                           ~(SA11X0_DCACHE_LINESIZE_BYTES - 1))

/*
 * SA-1100 Coprocessor 15 Extensions Register Definitions
 */
#ifdef __ASSEMBLER__
#  define SA11X0_READ_PROCESS_ID_REGISTER        c13
#  define SA11X0_WRITE_PROCESS_ID_REGISTER       c13
#  define SA11X0_READ_BREAKPOINT_REGISTER        c14
#  define SA11X0_WRITE_BREAKPOINT_REGISTER       c14
#  define SA11X0_TEST_CLOCK_AND_IDLE_REGISTER    c15
#else /* __ASSEMBLER__ */
#  define SA11X0_READ_PROCESS_ID_REGISTER        "c13"
#  define SA11X0_WRITE_PROCESS_ID_REGISTER       "c13"
#  define SA11X0_READ_BREAKPOINT_REGISTER        "c14"
#  define SA11X0_WRITE_BREAKPOINT_REGISTER       "c14"
#  define SA11X0_TEST_CLOCK_AND_IDLE_REGISTER    "c15"
#endif /* __ASSEMBLER__ */

/*
 * SA-1100 Process ID Virtual Address Mapping Definitions
 */
#ifdef __ASSEMBLER__
#  define SA11X0_ACCESS_PROC_ID_REGISTER_OPCODE  0x0
#  define SA11X0_ACCESS_PROC_ID_REGISTER_RM      c0
#else /* __ASSEMBLER__ */
#  define SA11X0_ACCESS_PROC_ID_REGISTER_OPCODE  "0x0"
#  define SA11X0_ACCESS_PROC_ID_REGISTER_RM      "c0"
#endif /* __ASSEMBLER__ */

#define SA11X0_PROCESS_ID_PID_MASK               0x7E000000

/*
 * SA-1100 Debug Support Definitions
 */
#ifdef __ASSEMBLER__
#  define SA11X0_ACCESS_DBAR_OPCODE              0x0
#  define SA11X0_ACCESS_DBAR_RM                  c0
#  define SA11X0_ACCESS_DBVR_OPCODE              0x0
#  define SA11X0_ACCESS_DBVR_RM                  c1
#  define SA11X0_ACCESS_DBMR_OPCODE              0x0
#  define SA11X0_ACCESS_DBMR_RM                  c2
#  define SA11X0_LOAD_DBCR_OPCODE                0x0
#  define SA11X0_LOAD_DBCR_RM                    c3
#else /* __ASSEMBLER__ */
#  define SA11X0_ACCESS_DBAR_OPCODE              "0x0"
#  define SA11X0_ACCESS_DBAR_RM                  "c0"
#  define SA11X0_ACCESS_DBVR_OPCODE              "0x0"
#  define SA11X0_ACCESS_DBVR_RM                  "c1"
#  define SA11X0_ACCESS_DBMR_OPCODE              "0x0"
#  define SA11X0_ACCESS_DBMR_RM                  "c2"
#  define SA11X0_LOAD_DBCR_OPCODE                "0x0"
#  define SA11X0_LOAD_DBCR_RM                    "c3"
#endif /* __ASSEMBLER__ */

#define SA11X0_DBCR_LOAD_WATCH_DISABLED          0x00000000
#define SA11X0_DBCR_LOAD_WATCH_ENABLED           0x00000001
#define SA11X0_DBCR_LOAD_WATCH_MASK              0x00000001
#define SA11X0_DBCR_STORE_ADDRESS_WATCH_DISABLED 0x00000000
#define SA11X0_DBCR_STORE_ADDRESS_WATCH_ENABLED  0x00000002
#define SA11X0_DBCR_STORE_ADDRESS_WATCH_MASK     0x00000002
#define SA11X0_DBCR_STORE_DATA_WATCH_DISABLED    0x00000000
#define SA11X0_DBCR_STORE_DATA_WATCH_ENABLED     0x00000004
#define SA11X0_DBCR_STORE_DATA_WATCH_MASK        0x00000004

#define SA11X0_IBCR_INSTRUCTION_ADDRESS_MASK     0xFFFFFFFC
#define SA11X0_IBCR_BREAKPOINT_DISABLED          0x00000000
#define SA11X0_IBCR_BREAKPOINT_ENABLED           0x00000001
#define SA11X0_IBCR_BREAKPOINT_ENABLE_MASK       0x00000001

/*
 * SA-1100 Test, Clock and Idle Control Definition
 */
#ifdef __ASSEMBLER__
#  define SA11X0_ICACHE_ODD_WORD_LOADING_OPCODE  0x1
#  define SA11X0_ICACHE_ODD_WORD_LOADING_RM      c1
#  define SA11X0_ICACHE_EVEN_WORD_LOADING_OPCODE 0x1
#  define SA11X0_ICACHE_EVEN_WORD_LOADING_RM     c2
#  define SA11X0_ICACHE_CLEAR_LFSR_OPCODE        0x1
#  define SA11X0_ICACHE_CLEAR_LFSR_RM            c4
#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_OPCODE   0x1
#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_RM       c8
#  define SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE   0x2
#  define SA11X0_ENABLE_CLOCK_SWITCHING_RM       c1
#  define SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE  0x2
#  define SA11X0_DISABLE_CLOCK_SWITCHING_RM      c2
#  define SA11X0_WAIT_FOR_INTERRUPT_OPCODE       0x2
#  define SA11X0_WAIT_FOR_INTERRUPT_RM           c8
#else /* __ASSEMBLER__ */
#  define SA11X0_ICACHE_ODD_WORD_LOADING_OPCODE  "0x1"
#  define SA11X0_ICACHE_ODD_WORD_LOADING_RM      "c1"
#  define SA11X0_ICACHE_EVEN_WORD_LOADING_OPCODE "0x1"
#  define SA11X0_ICACHE_EVEN_WORD_LOADING_RM     "c2"
#  define SA11X0_ICACHE_CLEAR_LFSR_OPCODE        "0x1"
#  define SA11X0_ICACHE_CLEAR_LFSR_RM            "c4"
#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_OPCODE   "0x1"
#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_RM       "c8"
#  define SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE   "0x2"
#  define SA11X0_ENABLE_CLOCK_SWITCHING_RM       "c1"
#  define SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE  "0x2"
#  define SA11X0_DISABLE_CLOCK_SWITCHING_RM      "c2"
#  define SA11X0_WAIT_FOR_INTERRUPT_OPCODE       "0x2"
#  define SA11X0_WAIT_FOR_INTERRUPT_RM           "c8"
#endif /* __ASSEMBLER__ */


/*
 * SA11X0 IRQ Controller IRQ Numbers
 */
#define SA11X0_IRQ_MIN                           0
                                                 
#define SA11X0_IRQ_GPIO_0_EDGE_DETECT            0
#define SA11X0_IRQ_GPIO_1_EDGE_DETECT            1
#define SA11X0_IRQ_GPIO_2_EDGE_DETECT            2
#define SA11X0_IRQ_GPIO_3_EDGE_DETECT            3
#define SA11X0_IRQ_GPIO_4_EDGE_DETECT            4
#define SA11X0_IRQ_GPIO_5_EDGE_DETECT            5
#define SA11X0_IRQ_GPIO_6_EDGE_DETECT            6
#define SA11X0_IRQ_GPIO_7_EDGE_DETECT            7
#define SA11X0_IRQ_GPIO_8_EDGE_DETECT            8
#define SA11X0_IRQ_GPIO_9_EDGE_DETECT            9
#define SA11X0_IRQ_GPIO_10_EDGE_DETECT           10
#define SA11X0_IRQ_GPIO_ANY_EDGE_DETECT          11
#define SA11X0_IRQ_LCD_CONT_SERVICE_REQUEST      12
#define SA11X0_IRQ_USB_SERVICE_REQUEST           13
#define SA11X0_IRQ_SDLC_SERVICE_REQUEST          14
#define SA11X0_IRQ_UART1_SERVICE_REQUEST         15
#define SA11X0_IRQ_ICP_SERVICE_REQUEST           16
#define SA11X0_IRQ_UART3_SERVICE_REQUEST         17
#define SA11X0_IRQ_MCP_SERVICE_REQUEST           18
#define SA11X0_IRQ_SSP_SERVICE_REQUEST           19
#define SA11X0_IRQ_CHANNEL_0_SERVICE_REQUEST     20
#define SA11X0_IRQ_CHANNEL_1_SERVICE_REQUEST     21
#define SA11X0_IRQ_CHANNEL_2_SERVICE_REQUEST     22
#define SA11X0_IRQ_CHANNEL_3_SERVICE_REQUEST     23