📄 ixdp2400_pci.c
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#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i));
#endif
}
/* Program MA/BA/RAS#/CAS#/WE# pull-up and pull-down Slew Lookup table registers */
/* (cr0_dctlpslew0 - cr0_dctlpslew3) and (cr0_dctlnslew0 - cr0_dctlnslew3) */
for(i = (DRAM_CH0_BASE_FRM_PCI + 0x198); i <= (DRAM_CH0_BASE_FRM_PCI + 0x1D0); i += 8)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i)) = 0xcccccccc;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i));
#endif
}
/* Program RCV pull-up and pull-down Slew Lookup table registers */
/* (cr0_drcvpslew0 - cr0_drcvpslew3) and (cr0_drcvnslew0 - cr0_drcvnslew3) */
for(i = (DRAM_CH0_BASE_FRM_PCI + 0x1E0); i <= (DRAM_CH0_BASE_FRM_PCI + 0x218); i += 8)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i)) = 0xcccccccc;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i));
#endif
}
/* Program CKE x8 pull-up and pull-down Slew Lookup table registers */
/* (cr0_dckex8pslew0 - cr0_dckex8pslew3) and (cr0_dckex8nslew0 - cr0_dckex8nslew3) */
for(i = (DRAM_CH0_BASE_FRM_PCI + 0x230); i <= (DRAM_CH0_BASE_FRM_PCI + 0x268); i += 8)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i)) = 0xcccccccc;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i));
#endif
}
/* Program CKE x16 pull-up and pull-down Slew Lookup table registers */
/* (cr0_dckex16pslew0 - cr0_dckex16pslew3) and (cr0_dckex16nslew0 - cr0_dckex16nslew3) */
for(i = (DRAM_CH0_BASE_FRM_PCI + 0x270); i <= (DRAM_CH0_BASE_FRM_PCI + 0x2A8); i += 8)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i)) = 0xcccccccc;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i));
#endif
}
/* Program CS# x8 pull-up and pull-down Slew Lookup table registers */
/* (cr0_dcsx8pslew0 - cr0_dcsx8pslew3) and (cr0_dcsx8nslew0 - cr0_dcsx8nslew3) */
for(i = (DRAM_CH0_BASE_FRM_PCI + 0x2B8); i <= (DRAM_CH0_BASE_FRM_PCI + 0x2F0); i += 8)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i)) = 0xcccccccc;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i));
#endif
}
/* Program CS# x16 pull-up and pull-down Slew Lookup table registers */
/* (cr0_dcsx16pslew0 - cr0_dcsx16pslew3) and (cr0_dcsx16nslew0 - cr0_dcsx16nslew3) */
for(i = (DRAM_CH0_BASE_FRM_PCI + 0x2F8); i <= (DRAM_CH0_BASE_FRM_PCI + 0x330); i += 8)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i)) = 0xcccccccc;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i));
#endif
}
/* Program CK CK# x8 pull-up and pull-down Slew Lookup table registers */
/* (cr0_dckx8pslew0 - cr0_dckx8pslew3) and (cr0_dckx8nslew0 - cr0_dckx8nslew3) */
for(i = (DRAM_CH0_BASE_FRM_PCI + 0x340); i <= (DRAM_CH0_BASE_FRM_PCI + 0x378); i += 8)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i)) = 0xcccccccc;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i));
#endif
}
/* Program CK CK# x16 pull-up and pull-down Slew Lookup table registers */
/* (cr0_dckx16pslew0 - cr0_dckx16pslew3) and (cr0_dckx16nslew0 - cr0_dckx16nslew3) */
for(i = (DRAM_CH0_BASE_FRM_PCI + 0x380); i <= (DRAM_CH0_BASE_FRM_PCI + 0x3B8); i += 8)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i)) = 0xcccccccc;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + i));
#endif
}
/* Flag Slew Programmed register as done */
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_SLEWPROGRAMMED_FRM_PCI)) = 0x1;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_SLEWPROGRAMMED_FRM_PCI));
#endif
/* Force SM Rcomp */
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_FRCSMRCOMP_FRM_PCI)) = 0x1;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_FRCSMRCOMP_FRM_PCI));
#endif
hal_delay_us(1000);
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_FRCSMRCOMP_FRM_PCI)) = 0x0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_FRCSMRCOMP_FRM_PCI));
#endif
/* cr0_ovrrideh: turn off h override, 0x0 */
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_OVRRIDEH_FRM_PCI)) = 0x0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_OVRRIDEH_FRM_PCI));
#endif
/* cr0_ovrridev: turn off v override, 0x0 */
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_OVRRIDEV_FRM_PCI)) = 0x0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_OVRRIDEV_FRM_PCI));
#endif
/* De-Select Test Mode (cr0_jt_config)
// User Overide RCOMP settings */
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_JT_CONFIG_FRM_PCI)) = 0x0;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + CR0_JT_CONFIG_FRM_PCI));
#endif
hal_delay_us(1000); // 1ms
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_CONTROL_FRM_PCI)) = *DU_CONTROL_REG;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_CONTROL_FRM_PCI));
#endif
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) = CKE;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI));
#endif
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) = (PRECHARGE | SIDE1 | SIDE0 | PRECHARGE_ALL);
while(*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) & PRECHARGE)
hal_delay_us(1000); // 1ms
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) = (LD_MODE_REG | SIDE1 | SIDE0 | EXT_LD_MODE);
while(*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) & LD_MODE_REG)
hal_delay_us(1000); // 1ms
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) = (LD_MODE_REG | SIDE1 | SIDE0 | RESET_DLL);
while(*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) & LD_MODE_REG)
hal_delay_us(1000); // 1ms
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) = (PRECHARGE | SIDE1 | SIDE0 | PRECHARGE_ALL);
while(*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) & PRECHARGE)
hal_delay_us(1000); // 1ms
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) = (REFRESH | SIDE1 | SIDE0);
while(*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) & REFRESH)
hal_delay_us(1000); // 1ms
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) = (REFRESH | SIDE1 | SIDE0);
while(*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) & REFRESH)
hal_delay_us(1000); // 1ms
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) = (LD_MODE_REG | SIDE1 | SIDE0 | LOAD_MODE_NORMAL);
while(*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_INIT_FRM_PCI)) & LD_MODE_REG)
hal_delay_us(1000); // 1ms
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_ECC_TEST_FRM_PCI)) |= DISABLE_CHK;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + DU_ECC_TEST_FRM_PCI));
#endif
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + MISC_CONTROL_FRM_PCI)) |= FLASH_ALIAS_DISABLE;
#ifdef A0_REV
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + MISC_CONTROL_FRM_PCI));
#endif
*(PCI_ADDR_EXT_REG) = (slave_dev_info.base_address[SDRAM_BAR] & 0xE0000000) >> 16;
// check slave's SDRAM
for(i = 0; i < 0x100000; i = i + 4)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + i)) = 0x5A5A5A5A;
// read it back
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + i));
if(temp != 0x5A5A5A5A)
{
printf("Slave SDRAM POST failed. addr = 0x%08X, actual = 0x%08X, expected = 0x5A5A5A5A\n", i, temp);
slave_sdram_passed = 0;
break;
}
}
if(slave_sdram_passed)
{
cyg_uint32 sdram_data_end, sdram_data_start, flash_data_start;
sdram_data_end = (cyg_uint32)&__ram_data_end;
sdram_data_start = (cyg_uint32)&__ram_data_start;
flash_data_start = (cyg_uint32)&__rom_data_start;
// now download BM to slave's SDRAM.
printf("Slave SDRAM POST passed\n");
*(SP_FRM_REG) = USE_32_BIT_DATA;
// copy the text section
for(i = 0; i < CYGMEM_REGION_rom_SIZE; i = i + 4)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + i)) = *((volatile cyg_uint32 *)(SLOW_PORT_BASE + i));
#ifdef A0_REV
// read it back to prevent PCI Mem bug
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + i));
#endif
}
// copy the data section
for(i = 0; i < (sdram_data_end - sdram_data_start); i = i + 4)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + sdram_data_start + i)) = *((volatile cyg_uint32 *)(SLOW_PORT_BASE + flash_data_start + i));
#ifdef A0_REV
// read it back to prevent PCI Mem bug
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + sdram_data_start + i));
#endif
}
// scrub only 1M
for(i = sdram_data_end; i < 0x100000; i = i + 4)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + i)) = 0;
#ifdef A0_REV
// read it back to prevent PCI Mem bug
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + i));
#endif
}
*(SP_FRM_REG) = USE_8_BIT_DATA;
// copy flash config
for(i = 0; i < MAX_CONFIG_DATA; i = i + 4)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + (cyg_uint32)&config + i)) = *((volatile cyg_uint32 *)((cyg_uint32)&config + i));
#ifdef A0_REV
// read it back to prevent PCI Mem bug
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + (cyg_uint32)&config + i));
#endif
}
*((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + SLAVE_POST_FLAG_LOC)) = 0;
*(PCI_ADDR_EXT_REG) = (slave_dev_info.base_address[CSR_BAR] & 0xE0000000) >> 16;
// final step - take slave out of reset and I am done with slave.
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + IXP_RESET0_FRM_PCI)) &= ~(RESET_XSCALE);
}
}
// now wait to see if slave completes its POST
*(PCI_ADDR_EXT_REG) = (slave_dev_info.base_address[SDRAM_BAR] & 0xE0000000) >> 16;
i = 0;
printf("Waiting for slave to complete POST.");
while(*((volatile cyg_uint32 *)(slave_dev_info.base_map[SDRAM_BAR] + SLAVE_POST_FLAG_LOC)) != POST_DONE)
{
// wait for 2s max
if(i > 4)
{
printf("\nSlave POST failed");
break;
}
// wait for 500ms
hal_delay_us(500000);
printf(".");
i++;
}
printf("\n");
// copy config data to slave's SRAM
if(board_config_data->config_valid == CONFIG_DATA_VALID)
{
*(PCI_ADDR_EXT_REG) = (slave_dev_info.base_address[CSR_BAR] & 0xE0000000) >> 16;
for(i = 0; i < sizeof(struct board_config); i = i + 4)
{
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + SCRATCH_BASE_FRM_PCI + i)) = *((volatile cyg_uint32 *)((cyg_uint32)board_config_data + i));
#ifdef A0_REV
// read it back to prevent PCI Mem bug
temp = *((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + SCRATCH_BASE_FRM_PCI + i));
#endif
}
}
#ifdef __ARMEB__
/* 82559 is LE. So, now I need to clear byte swapping bits so that when 82559 talks to IXP2400
pci unit does byte swapping */
*(PCI_ADDR_EXT_REG) = (slave_dev_info.base_address[CSR_BAR] & 0xE0000000) >> 16;
*((volatile cyg_uint32 *)(slave_dev_info.base_map[CSR_BAR] + PCI_CONTROL_FRM_PCI)) &= ~(PCI_CONTROL_BE_DEO | PCI_CONTROL_BE_DEI | PCI_CONTROL_BE_BEO | PCI_CONTROL_BE_BEI);
*(PCI_CONTROL_REG) &= ~(PCI_CONTROL_BE_DEO | PCI_CONTROL_BE_DEI | PCI_CONTROL_BE_BEO | PCI_CONTROL_BE_BEI);
#endif
return;
}
CYG_PCI_ADDRESS64 force_pci_alloc_mem(CYG_PCI_ADDRESS64 *base, int *addr_ext, cyg_uint32 size)
{
CYG_PCI_ADDRESS64 aligned_addr;
if(size >= 0x8000000)
{
(*addr_ext)++;
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